Reset Source Identification Register (Rsir - 0Xe01F C180) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

3.10.1 Reset Source Identification Register (RSIR - 0xE01F C180)

This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
Table 27:
Bit
0
1
2
7:3
User manual
external
reset
watchdog
reset
power
down
EINT0 wake-up
EINT1 wake-up
EINT2 wake-up
Fig 10. Reset block diagram including the wake-up timer
Reset Source identification Register (RSIR - address 0xE01F C180) bit description
Symbol Description
POR Power-On Reset (POR) event sets this bit, and clears all of the other bits
in this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
EXTR Assertion of the RESET signal sets this bit. This bit is cleared by POR,
but is not affected by WDT reset.
WDTR This bit is set when the watchdog timer times out and the WDTRESET
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
Chapter 3: System control block
C
Q
S
WAKE-UP TIMER
START
oscillator
output (F )
OSC
write "1"
from APB
Reset
PLL
UM10161
reset to the
on-chip circuitry
reset to
PCON.PD
n
COUNT 2
C
Q
S
ABP read of
PDBIT
in PCON
F
OSC
to CPU
Reset
value
see text
see text
see text
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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