User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
22.2Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status 'Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
22.4 Tables
Table 1: LPC2101/02/03 device information. . . . . . . . . . .4
Table 2: APB peripheries and base addresses . . . . . . .11
Table 3: ARM exception vector locations . . . . . . . . . . . .12
Table 4: LPC2101/02/03 memory mapping modes . . . .12
Table 5: Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6: Summary of system control registers . . . . . . . .16
Table 7: Recommended values for C
mode (crystal and external components
parameters) . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 8: External interrupt registers . . . . . . . . . . . . . . . .19
Table 9: External Interrupt Flag register (EXTINT - address
0xE01F C140) bit description . . . . . . . . . . . . . .20
Table 10: Interrupt Wake-up register (INTWAKE - address
0xE01F C144) bit description . . . . . . . . . . . . . .20
Table 11: External Interrupt Mode register (EXTMODE -
address 0xE01F C148) bit description . . . . . . .21
Table 12: External Interrupt Polarity register (EXTPOLAR -
address 0xE01F C14C) bit description. . . . . . .22
Table 13: System Control and Status flags register (SCS -
address 0xE01F C1A0) bit description . . . . . . .23
Table 14: Memory Mapping control register (MEMMAP -
address 0xE01F C040) bit description . . . . . . .23
Table 15: PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 16: PLL Control register (PLLCON - address
0xE01F C080) bit description . . . . . . . . . . . . . .27
Table 17: PLL Configuration register (PLLCFG - address
0xE01F C084) bit description . . . . . . . . . . . . . .27
Table 18: PLL Status register (PLLSTAT - address
0xE01F C088) bit description . . . . . . . . . . . . . .28
Table 19: PLL Control bit combinations . . . . . . . . . . . . . .28
Table 20: PLL Feed register (PLLFEED - address
0xE01F C08C) bit description. . . . . . . . . . . . . .29
Table 21: Elements determining PLL's frequency. . . . . . .29
Table 22: PLL Divider values . . . . . . . . . . . . . . . . . . . . . .30
Table 23: PLL Multiplier values. . . . . . . . . . . . . . . . . . . . .30
Table 24: Power control registers . . . . . . . . . . . . . . . . . . .32
Table 25: Power Control register (PCON - address
0xE01F COCO) bit description . . . . . . . . . . . . .32
Table 26: Power Control for Peripherals register (PCONP -
address 0xE01F C0C4) bit description. . . . . . .33

User manual

products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
22.3Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I
Electronics N.V.
Table 27: Reset Source identification Register (RSIR -
Table 28: APB divider register map . . . . . . . . . . . . . . . . . 36
Table 29: APB Divider register (APBDIV - address
Table 30: MAM Responses to program accesses of various
in oscillation
X1/X2
Table 31: MAM responses to data and DMA accesses of
Table 32: Summary of MAM registers . . . . . . . . . . . . . . . 42
Table 33: MAM Control Register (MAMCR - address
Table 34: MAM Timing register (MAMTIM - address
Table 35: VIC register map . . . . . . . . . . . . . . . . . . . . . . . 45
Table 36: Software Interrupt register (VICSoftInt - address
Table 37: Software Interrupt register (VICSoftInt - address
Table 38: Software Interrupt Clear register (VICSoftIntClear
Table 39: Software Interrupt Clear register (VICSoftIntClear
Table 40: Raw Interrupt status register (VICRawIntr -
Table 41: Raw Interrupt status register (VICRawIntr -
Table 42: Interrupt Enable register (VICIntEnable - address
Table 43: Interrupt Enable register (VICIntEnable - address
Table 44: Software Interrupt Clear register (VICIntEnClear -
Table 45: Software Interrupt Clear register (VICIntEnClear -
Table 46: Interrupt Select register (VICIntSelect - address
Table 47: Interrupt Select register (VICIntSelect - address
Table 48: IRQ Status register (VICIRQStatus - address
Rev. 01 — 12 January 2006
Chapter 22: Supplementary information
2
C-bus — wordmark and logo are trademarks of Koninklijke Philips
address 0xE01F C180) bit description. . . . . . . 35
0xE01F C100) bit description. . . . . . . . . . . . . . 36
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
various types . . . . . . . . . . . . . . . . . . . . . . . . . . 42
0xE01F C000) bit description. . . . . . . . . . . . . . 43
0xE01F C004) bit description. . . . . . . . . . . . . . 43
0xFFFF F018) bit allocation . . . . . . . . . . . . . . 46
0xFFFF F018) bit description. . . . . . . . . . . . . . 47
- address 0xFFFF F01C) bit allocation . . . . . . 47
- address 0xFFFF F01C) bit description . . . . . 47
address 0xFFFF F008) bit allocation . . . . . . . 48
address 0xFFFF F008) bit description . . . . . . . 48
0xFFFF F010) bit allocation . . . . . . . . . . . . . . 48
0xFFFF F010) bit description. . . . . . . . . . . . . . 49
address 0xFFFF F014) bit allocation . . . . . . . 49
address 0xFFFF F014) bit description . . . . . . . 49
0xFFFF F00C) bit allocation . . . . . . . . . . . . . . 49
0xFFFF F00C) bit description . . . . . . . . . . . . . 50
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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