Fiq Status Register (Vicfiqstatus - 0Xffff F004); Vector Control Registers 0-15 (Vicvectcntl0-15 - 0Xffff F200-23C) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

5.4.8 FIQ Status register (VICFIQStatus - 0xFFFF F004)

This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as FIQ. If more than one request is classified as FIQ, the
FIQ service routine can read this register to see which request(s) is (are) active.
Table 50: FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol -
Access RO
Bit 23
Symbol -
Access RO
Bit 15
Symbol EINT1
Access RO
Bit 7
Symbol UART1
Access RO
Table 51: FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description
Bit Symbol
31:0 See
VICFIQStatus
bit allocation
table.

5.4.9 Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C)

These are a read/write accessible registers. Each of these registers controls one of the 16
vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Note that
disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the
interrupt itself, the interrupt is simply changed to the non-vectored form.
Table 52: Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C) bit description
Bit Symbol
4:0 int_request/
sw_int_assig
5 IRQslot_en
31:6 -
User manual
30 29
- -
RO RO
22 21
- -
RO RO
14 13
EINT0 RTC
RO RO
6 5
UART0 TIMER1
RO RO
Description
A bit read as 1 indicates a corresponding interrupt request being enabled,
classified as FIQ, and asserted
Description
The number of the interrupt request or software interrupt assigned to this
vectored IRQ slot. As a matter of good programming practice, software should
not assign the same interrupt number to more than one enabled vectored IRQ
slot. But if this does occur, the lower numbered slot will be used when the
interrupt request or software interrupt is enabled, classified as IRQ, and
asserted.
When 1, this vectored IRQ slot is enabled, and can produce a unique ISR
address when its assigned interrupt request or software interrupt is enabled,
classified as IRQ, and asserted.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Rev. 01 — 12 January 2006
28 27
- TIMER3
RO RO
20 19
- I2C1
RO RO
12 11
PLL SSP/SPI1
RO RO
4 3
TIMER0 ARMCore1
RO RO
UM10161
Chapter 5: VIC
26 25
TIMER2 -
RO RO
18 17
AD0 -
RO RO
10 9
SPI0 I2C0
RO RO
2 1
ARMCore0 -
RO RO
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
24
-
RO
16
EINT2
RO
8
-0
RO
0
WDT
RO
Reset
value
0
Reset
value
0
0
NA
51