Uart1 Fractional Divider Register (U1Fdr - 0Xe001 0028); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 101: UART1 Divisor Latch LSB register (U1DLL - address 0xE001 0000, when
Bit
7:0
Table 102: UART1 Divisor Latch MSB register (U1DLM - address 0xE001 0004, when
Bit
7:0

10.3.4 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)

The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at user's discretion. This pre-scaler takes the
APB clock and generates an output clock per specified fractional requirements.
Table 103: UART1 Fractional Divider Register (U1FDR - address 0xE001 0028) bit description
Bit
3:0
7:4
31:8 -
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART1 disabled making sure that UART1 is
fully software and hardware compatible with UARTs not equipped with this feature.
UART1 baudrate can be calculated as:
Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud
rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:

User manual

DLAB = 1) bit description
Symbol Description
DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM
register, determines the baud rate of the UART1.
DLAB = 1) bit description
Symbol Description
DLMSB The UART1 Divisor Latch MSB Register, along with the U1DLL
register, determines the baud rate of the UART1.
Function Description
DIVADDVAL Baudrate generation pre-scaler divisor value. If this field is 0,
fractional baudrate generator will not impact the UART1
baudrate.
MULVAL Baudrate pre-scaler multiplier value. This field must be greater
or equal 1 for UART1 to operate properly, regardless of
whether the fractional baudrate generator is used or not.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
UART1
baudrate
1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 15
Rev. 01 — 12 January 2006
= -------------------------------------------------------------------------------------------------------------------------------
× ( ×
16 16 U1DLM + U1DLL
UM10161
Chapter 10: UART1
PCLK
⎛
DivAddVal
) ×
1 +
---------------------------- -
⎝
MulVal
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset value
0x01
Reset value
0x00
Reset value
0
1
NA
(4)
⎞
⎠
102