Table 78: Uart0 Interrupt Enable Register Bit Descriptions (U0Ier - 0Xe000C004 When Dlab = 0); Table 79: Uart0 Interrupt Identification Register Bit Descriptions (U0Iir - 0Xe000C008, Read Only) - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
UART0 Interrupt Enable Register (U0IER - 0xE000C004 when DLAB = 0)
The U0IER is used to enable the four UART0 interrupt sources.
Table 79: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0)
U0IER Function
RBR Interrupt
0
Enable
THRE Interrupt
1
Enable
Rx Line Status
2
Interrupt Enable
7:3 Reserved
UART0 Interrupt Identification Register (U0IIR - 0xE000C008, Read Only)
The U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an
U0IIR access. If an interrupt occurs during an U0IIR access, the interrupt is recorded for the next U0IIR access.
Table 80: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0xE000C008, Read Only)
U0IIR Function
Interrupt
0
Pending
Interrupt
3:1
Identification
5:4 Reserved
7:6 FIFO Enable
Interrupts are handled as described in Table 81. Given the status of U0IIR[3:0], an interrupt handler routine can determine the
cause of the interrupt and how to clear the active interrupt. Interrupts are handled as described in Table 81. The U0IIR must be
read in order to clear the interrupt prior to exitting the Interrupt Service Routine.
UART0
0: Disable the RDA interrupt.
1: Enable the RDA interrupt.
U0IER0 enables the Receive Data Available interrupt for UART0. It also controls the
Character Receive Time-out interrupt.
0: Disable the THRE interrupt.
1: Enable the THRE interrupt.
U0IER1 enables the THRE interrupt for UART0. The status of this interrupt can be read
from U0LSR5.
0: Disable the Rx line status interrupts.
1: Enable the Rx line status interrupts.
U0IER2 enables the UART0 Rx line status interrupts. The status of this interrupt can be
read from U0LSR[4:1].
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
0: At least one interrupt is pending.
1: No pending interrupts.
Note that U0IIR0 is active low. The pending interrupt can be determined by evaluating
U0IER3:1.
011: 1. Receive Line Status (RLS)
010: 2a.Receive Data Available (RDA)
110: 2b.Character Time-out Indicator (CTI)
001: 3. THRE Interrupt.
U0IER3 identifies an interrupt corresponding to the UART0 Rx FIFO. All other
combinations of U0IER3:1 not listed above are reserved (000,100,101,111).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
These bits are equivalent to U0FCR0.
LPC2119/2129/2194/2292/2294
Description
Description
143
Preliminary User Manual
Reset
Value
0
0
0
NA
Reset
Value
1
0
NA
0
May 03, 2004