Uart1 Divisor Latch Registers 0 And 1 (U1Dll - 0Xe001 0000 And U1Dlm - 0Xe001 0004, When; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
10.3.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when
DLAB = 0 Read Only)
The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the "oldest" received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1RBR. The U1RBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U1LSR
register, and then to read a byte from the U1RBR.
Table 99:
Bit
7:0
10.3.2 UART1 Transmitter Holding Register (U1THR - 0xE001 0000, when
DLAB = 0 Write Only)
The U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1THR. The U1THR is always Write Only.
Table 100: UART1 Transmitter Holding Register (U1THR - address 0xE001 0000, when
Bit
7:0
10.3.3 UART1 Divisor Latch registers 0 and 1 (U1DLL - 0xE001 0000 and
U1DLM - 0xE001 0004, when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Fractional Baud Rate Generator and holds
the value used to divide the clock supplied by the fractional prescaler in order to produce
the baud rate clock, which must be 16x the desired baud rate
and U1DLM registers together form a 16 bit divisor where U1DLL contains the lower 8 bits
of the divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is
treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit
(DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches.
Details on how to select the right value for U1DLL and U1DLM can be found later on in
this chapter.

User manual

UART1 Receiver Buffer Register (U1RBR - address 0xE001 0000, when DLAB = 0
Read Only) bit description
Symbol Description
RBR The UART1 Receiver Buffer Register contains the oldest
received byte in the UART1 RX FIFO.
DLAB = 0 Write Only) bit description
Symbol Description
THR Writing to the UART1 Transmit Holding Register causes the data
to be stored in the UART1 transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
Rev. 01 — 12 January 2006
UM10161
Chapter 10: UART1
Reset value
undefined
Reset value
NA
(Equation 4). The U1DLL
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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