Uart0 Line Status Register; 0Xe000 C014, Read Only); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 92: UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description
Bit Symbol
2 Stop Bit Select
3 Parity Enable
5:4 Parity Select
6 Break Control
7 Divisor Latch
Access Bit (DLAB)
9.3.10 UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only)
The U0LSR is a read-only register that provides status information on the UART0 TX and
RX blocks.
Table 93: UART0 Line Status Register (U0LSR - address 0xE000 C014, read only) bit description
Bit Symbol Value Description
0 Receiver Data
Ready
(RDR)
0
1
1 Overrun Error
(OE)
0
1
2 Parity Error
(PE)
0
1

User manual

Value Description
0 1 stop bit.
1 2 stop bits (1.5 if U0LCR[1:0]=00).
0 Disable parity generation and checking.
1 Enable parity generation and checking.
00 Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
0 Disable break transmission.
1 Enable break transmission. Output pin UART0 TXD is forced to
logic 0 when U0LCR[6] is active HIGH.
0 Disable access to Divisor Latches.
1 Enable access to Divisor Latches.
U0LSR0 is set when the U0RBR holds an unread character and is cleared
when the UART0 RBR FIFO is empty.
U0RBR is empty.
U0RBR contains valid data.
The overrun error condition is set as soon as it occurs. An U0LSR read clears
U0LSR1. U0LSR1 is set when UART0 RSR has a new character assembled
and the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will not
be overwritten and the character in the UART0 RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
When the parity bit of a received character is in the wrong state, a parity error
occurs. An U0LSR read clears U0LSR[2]. Time of parity error detection is
dependent on U0FCR[0].
Note: A parity error is associated with the character at the top of the UART0
RBR FIFO.
Parity error status is inactive.
Parity error status is active.
Rev. 01 — 12 January 2006
UM10161
Chapter 9: UART0
Reset value
0
0
0
0
0
Reset value
0
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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