Philips LPC2101 User Manual page 11

Philips Semiconductors
Volume 1
Table 2:
APB peripheral
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 - 22
23
24
25
26
27
28
29
30 - 126
127
2.2 LPC2101/02/03 memory re-mapping and boot block
2.2.1 Memory map concepts and operating modes
The basic concept on the LPC2101/02/03 is that each memory area has a "natural"
location in the memory map. This is the address range for which code residing in that area
is written. The bulk of each memory space remains permanently fixed in the same
location, eliminating the need to have portions of the code designed to run in different
address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in
Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the different operating modes described in
interrupts is accomplished via the Memory Mapping Control feature
mapping control" on page
User manual
APB peripheries and base addresses
Base address
0xE000 0000
0xE000 4000
0xE000 8000
0xE000 C000
0xE001 0000
0xE001 4000
0xE001 8000
0xE001 C000
0xE002 0000
0xE002 4000
0xE002 8000
0xE002 C000
0xE003 0000
0xE003 4000
0xE003 8000
0xE005 8000
0xE005 C000
0xE006 0000
0xE006 4000
0xE006 8000
0xE006 C000
0xE007 0000
0xE007 4000
0xE007 8000
0xE01F 8000
0xE01F C000
23).
Rev. 01 — 12 January 2006
Peripheral name
Watchdog timer
Timer 0
Timer 1
UART0
UART1
Not used
Not used
2
I C0
SPI0
RTC
GPIO
Pin connect block
Not used
ADC
Not used
2
I C1
Not used
Not used
SSP
Timer 3
Timer 4
Not used
System Control Block
Table 3 below), a small portion of the
Table
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 2: Memory map
4. Re-mapping of the
(Section 3.7 "Memory
11