Raw Interrupt Status Register; 0Xffff F008); 0Xffff F010) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
5.4.3 Raw Interrupt status register (VICRawIntr - 0xFFFF F008)
This is a read only register. This register reads out the state of the 32 interrupt requests
and software interrupts, regardless of enabling or classification.
Table 40: Raw Interrupt status register (VICRawIntr - address 0xFFFF F008) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol -
Access RO
Bit 23
Symbol -
Access RO
Bit 15
Symbol EINT1
Access RO
Bit 7
Symbol UART1
Access RO
Table 41: Raw Interrupt status register (VICRawIntr - address 0xFFFF F008) bit description
Bit Symbol
31:0 See
VICRawIntr bit
allocation
table.
5.4.4 Interrupt Enable register (VICIntEnable - 0xFFFF F010)
This is a read/write accessible register. This register controls which of the 32 interrupt
requests and software interrupts contribute to FIQ or IRQ.
Table 42: Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol -
Access R/W
Bit 23
Symbol -
Access R/W
Bit 15
Symbol EINT1
Access R/W
Bit 7
Symbol UART1
Access R/W
User manual
30 29
- -
RO RO
22 21
- -
RO RO
14 13
EINT0 RTC
RO RO
6 5
UART0 TIMER1
RO RO
Value Description
0 The interrupt request or software interrupt with this bit number is
negated.
1 The interrupt request or software interrupt with this bit number is
negated.
30 29
- -
R/W R/W
22 21
- -
R/W R/W
14 13
EINT0 RTC
R/W R/W
6 5
UART0 TIMER1
R/W R/W
Rev. 01 — 12 January 2006
28 27
- TIMER3
RO RO
20 19
- I2C1
RO RO
12 11
PLL SSP/SPI1
RO RO
4 3
TIMER0 ARMCore1
RO RO
28 27
- TIMER3
R/W R/W
20 19
- I2C1
R/W R/W
12 11
PLL SSP/SPI1
R/W R/W
4 3
TIMER0 ARMCore1
R/W R/W
UM10161
Chapter 5: VIC
26 25
TIMER2 -
RO RO
18 17
AD0 -
RO RO
10 9
SPI0 I2C0
RO RO
2 1
ARMCore0 -
RO RO
26 25
TIMER2 -
R/W R/W
18 17
AD0 -
R/W R/W
10 9
SPI0 I2C0
R/W R/W
2 1
ARMCore0 -
R/W R/W
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
24
-
RO
16
EINT2
RO
8
-
RO
0
WDT
RO
Reset
value
0
24
-
R/W
16
EINT2
R/W
8
-
R/W
0
WDT
R/W
48