Ssp Control Register 1 (Sspcr1 - 0Xe006 8004); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 148: SSP Control Register 0 (SSPCR0 - address 0xE006 8000) bit description
Bit
6
7
15:8

13.4.2 SSP Control Register 1 (SSPCR1 - 0xE006 8004)

This register controls certain aspects of the operation of the SSP controller.
Table 149: SSP Control Register 1 (SSPCR1 - address 0xE006 8004) bit description
Bit
0
1
2
3
7:4

User manual

Symbol Value Description
CPOL Clock Out Polarity. This bit is only used in SPI mode.
SSP controller captures serial data on the first clock transition
0
of the frame, that is, the transition away from the inter-frame
state of the clock line.
1 SSP controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
CPHA Clock Out Phase. This bit is only used in SPI mode.
0 SSP controller maintains the bus clock low between frames.
1 SSP controller maintains the bus clock high between frames.
SCR Serial Clock Rate. The number of prescaler-output clocks per
bit on the bus, minus one. Given that CPSDVR is the prescale
divider, and the APB clock PCLK clocks the prescaler, the bit
frequency is PCLK / (CPSDVSR * [SCR+1]).
Symbol Value Description
LBM Loop Back Mode.
0 During normal operation.
1 Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).
SSE SSP Enable.
0 The SSP controller is disabled.
1 The SSP controller will interact with other devices on the
serial bus. Software should write the appropriate control
information to the other SSP registers and interrupt
controller registers, before setting this bit.
MS Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
The SSP controller acts as a master on the bus, driving the
0 SCLK, MOSI, and SSEL lines and receiving the MISO line.
1 The SSP controller acts as a slave on the bus, driving
MISO line and receiving SCLK, MOSI, and SSEL lines.
SOD Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SSP controller
from driving the transmit data line (MISO).
- Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 13: SSP
Reset
value
0
0
0
0
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
0
0x00
176