Uart1 Line Control Register (U1Lcr - 0Xe001 000C); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 108: UART1 FIFO Control Register (U1FCR - address 0xE001 0008) bit description
Bit Symbol
0 FIFO Enable
1 RX FIFO Reset
2 TX FIFO Reset
5:3 -
7:6 RX Trigger Level

10.3.9 UART1 Line Control Register (U1LCR - 0xE001 000C)

The U1LCR determines the format of the data character that is to be transmitted or
received.
Table 109: UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description
Bit Symbol
1:0 Word Length
Select
2 Stop Bit Select
3 Parity Enable
5:4 Parity Select

User manual

Value Description
0 UART1 FIFOs are disabled. Must not be used in the application.
1 Active HIGH enable for both UART1 Rx and TX FIFOs and
U1FCR[7:1] access. This bit must be set for proper UART1
operation. Any transition on this bit will automatically clear the
UART1 FIFOs.
0 No impact on either of UART1 FIFOs.
1 Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx
FIFO and reset the pointer logic. This bit is self-clearing.
0 No impact on either of UART1 FIFOs.
1 Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX
FIFO and reset the pointer logic. This bit is self-clearing.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.
00 trigger level 0 (1 character or 0x01).
01 trigger level 1 (4 characters or 0x04).
10 trigger level 2 (8 characters or 0x08).
11 trigger level 3 (14 characters or 0x0E).
Value Description
00 5 bit character length.
01 6 bit character length.
10 7 bit character length.
11 8 bit character length.
0 1 stop bit.
1 2 stop bits (1.5 if U1LCR[1:0]=00).
0 Disable parity generation and checking.
1 Enable parity generation and checking.
00 Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
Rev. 01 — 12 January 2006
UM10161
Chapter 10: UART1
Reset value
0
0
0
NA
0
Reset value
0
0
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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