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Philips Semiconductors
Volume 1
Latch, and a 15-bit comparator associated with each buffer (prefetch, branch trail, and
data). Each 128-bit latch holds 4 words (4 ARM instructions, or 8 Thumb instructions).
Also associated with each buffer are 32 4:1 Multiplexers that select the requested word
from the 128-bit line.
Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data,
which are captured in the Data latch. This speeds up sequential Data operations, but has
little or no effect on random accesses.
4.3.3 Flash programming issues
Since the Flash memory does not allow accesses during programming and erase
operations, it is necessary for the MAM to force the CPU to wait if a memory access to a
Flash address is requested while the Flash module is busy. (This is accomplished by
asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay
could result in a watchdog time-out. The user will need to be aware of this possibility and
take steps to insure that an unwanted watchdog reset does not cause a system failure
while programming or erasing the Flash memory.
In order to preclude the possibility of stale data being read from the Flash memory, the
LPC2101/02/03 MAM holding latches are automatically invalidated at the beginning of any
Flash programming or erase operation. Any subsequent read from a Flash address will
cause a new fetch to be initiated after the Flash operation has completed.
4.4 MAM operating modes
Three modes of operation are defined for the MAM, trading off performance for ease of
predictability:
Table 30:
Program Memory Request Type
Sequential access, data in latches
Sequential access, data not in latches
Non-sequential access, data in latches
Non-sequential access, data not in latches Initiate Fetch
User manual
Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2
below). There are no instruction prefetches.
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see note 2 below). This means that
all branches cause memory fetches. All data operations cause a Flash read because
buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
MAM Responses to program accesses of various types
Rev. 01 — 12 January 2006
MAM Mode
0
1
[2]
Initiate Fetch
Use Latched
[1]
Data
Initiate Fetch
Initiate Fetch
[2]
Initiate Fetch
Initiate Fetch
Initiate Fetch
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 4: MAM Module
2
Use Latched
[1]
Data
[1]
[1]
Initiate Fetch
[1][2]
Use Latched
[1]
Data
[1]
[1]
Initiate Fetch
41
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