Power Control; Register Description - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Based on these specifications, M = CCLK / Fosc = 60 MHz / 10 MHz = 6. Consequently,
M - 1 = 5 will be written as PLLCFG[4:0].
Value for P can be derived from P = F
in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for
F
produces P = 2.67. The only solution for P that satisfies both of these requirements and is
listed in

3.9 Power control

The LPC2101/02/03 supports two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip pins remain static.
The Power-down mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
If the RTC is running with its external 32 kHz oscillator at the time of entry into
Power-down mode, operation can resume using an interrupt from the RTC (see
17.4.1 "RTC
Entry to Power-down and Idle modes must be coordinated with program execution.
Wake-up from Power-down or Idle modes via an interrupt resumes program execution in
such a way that no instructions are lost, incomplete, or repeated. Wake up from
Power-down mode is discussed further in
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.

3.9.1 Register description

The Power Control function contains two registers, as shown in
descriptions follow.
User manual
= 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest F
CCO
Table 22 is P = 2. Therefore, PLLCFG[6:5] = 1 will be used.
interrupts").
Rev. 01 — 12 January 2006
Chapter 3: System control block
/ (CCLK x 2), using condition that F
CCO
Section 3.12 "Wake-up timer" on page
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
must be
CCO
frequency criteria
CCO
Section
37.
Table 24. More detailed
31