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12.1 Features
12.2 Description
12.2.1 SPI overview
SPI is a full duplex serial interfaces. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bit of data to the slave, and the slave always sends a byte of data to the master.
12.2.2 SPI data transfers
Figure 39
are available with the SPI. This timing diagram illustrates a single 8 bit data transfer. The
first thing you should notice in this timing diagram is that it is divided into three horizontal
parts. The first part describes the SCK and SSEL signals. The second part describes the
MOSI and MISO signals when the CPHA variable is 0. The third part describes the MOSI
and MISO signals when the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with
CPOL set to both 0 and 1. The second point to note is the activation and de-activation of
the SSEL signal. When CPHA = 1, the SSEL signal will always go inactive between data
transfers. This is not guaranteed when CPHA = 0 (the signal can remain active).
User manual
UM10161
Chapter 12: SPI interface (SPI0)
Rev. 01 — 12 January 2006
•
Single complete and independent SPI controller
•
Compliant with Serial Peripheral Interface (SPI) specification
•
Synchronous, serial, full duplex communication
•
Combined SPI master and slave
•
Maximum data bit rate of one eighth of the input clock rate
•
8 to 16 bit per transfer
is a timing diagram that illustrates the four different data transfer formats that
Rev. 01 — 12 January 2006
User manual
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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