I 2 C Data Register; I 2 C Slave Address Register; I 2 C Scl High Duty Cycle Register; I 2 C Scl Low Duty Cycle Register - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
2
11.7.4 I
I2C1DAT - 0xE005 C008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 124: I
Bit Symbol
7:0 Data
2
11.7.5 I
I2C1, I2C1ADR - address 0xE005 C00C)
These registers are readable and writable, and is only used when an I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the general
call bit. When this bit is set, the general call address (0x00) is recognized.
Table 125: I
Bit Symbol
0
7:1 Address
2
11.7.6 I
0xE001 C010 and I2C1, I2C1SCLH - 0xE0015 C010)
Table 126: I
Bit
15:0
2
11.7.7 I
0xE001 C014; I2C1 - I2C1SCLL: 0xE0015 C014)
Table 127: I
Bit
15:0
11.7.8 Selecting the appropriate I
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of PCLK cycles for the SCL HIGH
time, I2SCLL defines the number of PCLK cycles for the SCL low time. The frequency is
determined by the following formula (PCLK is the frequency of the peripheral bus APB):

User manual

C Data register (I2DAT: I2C0, I2C0DAT - 0xE001 C008 and I2C1,
2
C Data register (I2DAT: I2C0, I2C0DAT - address 0xE001 C008 and I2C1, I2C1DAT
- address 0xE005 C008) bit description
Description
This register holds data values that have been received, or are to
be transmitted.
C Slave Address register (I2ADR: I2C0, I2C0ADR - 0xE001 C00C and
2
C Slave Address register (I2ADR: I2C0, I2C0ADR - address 0xE001 C00C and
I2C1, I2C1ADR - address 0xE005 C00C) bit description
Description
GC General Call enable bit.
2
The I C device address for slave mode.
C SCL HIGH duty cycle register (I2SCLH: I2C0, I2C0SCLH -
2
C SCL HIGH Duty Cycle register (I2SCLH: I2C0, I2C0SCLH - address
0xE001 C010 and I2C1, I2C1SCLH - address 0xE005 C010) bit description
Symbol Description
SCLH Count for SCL HIGH time period selection.
C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL:
2
C SCL Low Duty Cycle register (I2SCLL: I2C0, I2C0SCLL - address 0xE001 C014
and I2C1, I2C1SCLL - address 0xE005 C014) bit description
Symbol Description
SCLL Count for SCL low time period selection.
Rev. 01 — 12 January 2006
2
C data rate and duty cycle
UM10161
2
Chapter 11: I C interfaces
Reset value
0
2
C interface is set to
Reset value
0
0x00
Reset value
0x0004
Reset value
0x0004
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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