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Philips Semiconductors
ARM-based Microcontroller
UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only)
The U1RBR is the top byte of the UART1 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can
be read via the bus interface. The LSB (bit 0) represents the "oldest" received data bit. If the character received is less than 8
bits, the unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1RBR. The U1RBR is always Read Only.
Table 88: UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only)
U1RBR
Function
Receiver Buffer
7:0
Register
UART1 Transmitter Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only)
The U1THR is the top byte of the UART1 Tx FIFO. The top byte is the newest character in the Tx FIFO and can be written via
the bus interface. The LSB represents the first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1THR. The U1THR is always Write Only.
Table 89: UART1 Transmit Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only)
U1THR
Function
Transmit
7:0
Holding Register
UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1)
UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used to divide the VPB clock (pclk) in
order to produce the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM registers together form
a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor. A 'h0000
value is treated like a 'h0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR must be
one in order to access the UART1 Divisor Latches.
Table 90: UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1)
U1DLL
Function
Divisor Latch
7:0
LSB Register
UART1
The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 Rx
FIFO.
Writing to the UART1 Transmit Holding Register causes the data to be stored in the
UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and
the transmitter is available.
The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the
baud rate of the UART1.
LPC2119/2129/2194/2292/2294
Description
Description
Description
154
Preliminary User Manual
Reset
Value
un-
defined
Reset
Value
N/A
Reset
Value
0x01
May 03, 2004
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