ABB TPU2000 Technical Manual page 6

TPU2000/2000R Modbus/Modbus Plus Automation Guide
Table 5-34. 2 Winding Differential Fault Record Address Table ...........................................................................113
Table 5-35. 2 Winding Through Fault Register Definition for the TPU2000/TPU2000R.......................................115
Table 5-36. 3 Winding Through Fault Record Buffer Modbus Register Definition ................................................117
Table 5-37. 2 Winding Harmonic Restraint Fault Record Buffer Modbus Register Assignment...........................119
Table 5-38. 3 Winding Harmonic Fault Register Definitions..................................................................................121
Table 5-39. Operation Record Address Definition.................................................................................................124
Table 5-40. Event Record Definition Type ............................................................................................................124
Table 5-41. Security Status Register Indicating Password Requirement..............................................................127
Table 5-42. Group I Control Registers...................................................................................................................129
Table 5-43. Group II Bit Definitions for TPU2000R Control ..................................................................................133
Table 5-44. State Truth Chart for Physical Input Forcing Function .......................................................................134
Table 5-45. TPU2000R Bit Control Function Definitions .......................................................................................136
Table 5-46. State Truth Chart for Physical Input Forcing Function .......................................................................138
Table 5-47. ECP Default Correlation to Forced Logical Input Bit Map..................................................................140
Table 5-48. State Truth Chart for Physical Input Forcing Function .......................................................................142
Table 5-49. TPU2000 and TPU2000R Bit Control Function Definitions................................................................142
Table 5-50. State Truth Chart for Physical Input Forcing Function .......................................................................145
Table 5-51. TPU2000 and TPU2000R Bit Control Function Definitions................................................................145
Table 5-52. TPU2000 and TPU2000R Bit Control Function Definitions................................................................150
Table 5-53. Oscillographic Resolution Capabilities ...............................................................................................152
Table 5-54. Oscillographic Configuration Registers ..............................................................................................153
Table 5-55. Oscillographic Data Format Retrieval Block.......................................................................................156
Table 5-56. Physical Logical Function Byte Configuration Codes for Register 60044 to 60058 ..........................169
Table 5-57. Relay Configuration Setting Definition ...............................................................................................170
Table 5-58. Programmable Input "NEGATED" "AND" Input..................................................................................171
Table 5-59. AND/OR Conditional Logic Table.......................................................................................................172
Table 5-60. Physical Input Mapping Table ............................................................................................................173
Table 5-61. Relay Configuration Setting Definition ...............................................................................................174
Table 5-62. Physical Logical Function Byte Configuration Codes for Register 60044 to 60058 ..........................175
Table 5-63. Programmable Output AND/OR Select..............................................................................................178
Table 5-64. Programmable Output User Defined Strings......................................................................................178
Table 5-65. To Be Named .....................................................................................................................................179
Table 5-66. Primary Settings Register Definition Common to the 2 and 3 Winding Units ....................................180
Table 5-67. 3 Winding Primary Settings Block ......................................................................................................183
Table 5-68. ALT 1 Settings Register Definition .....................................................................................................185
Table 5-69. Alternate 1 Settings for 3 Winding Block............................................................................................188
Table 5-70. ALT 2 Settings Register Definition .....................................................................................................190
Table 5-71. Alternate 2 Settings for 3 Winding Block............................................................................................193
Table 5-72. TPU2000/2000R Configuration Settings Register Setting .................................................................194
Table 5-73. TPU2000/2000R Configuration Settings Register Setting .................................................................196
Table 5-74. Counter Register Assignment ............................................................................................................197
Table 5-75. Alarm Setting Table............................................................................................................................198
Table 5-76. 3 Winding Alarm Settings Block .........................................................................................................198
Table 5-77. Real Time Clock Register Definition Assignment ..............................................................................199
Table 5-78. ULO Table Map for Character Name Assignment .............................................................................199
Table 5-79. ULI Table Map for Character Name Assignment ...............................................................................201
Table 5-80. FLI Soft Bit Table Map and Character Name Assignment Register Map ..........................................202
Table 5-81. Modbus Plus Global Register Map Configuration Definition ..............................................................207
Table 5-82. User Definable Register Configuration Table.....................................................................................210
Table 5-83. Modbus Standard Exception Codes...................................................................................................228
Table 5-84. TPU2000/TPU2000R Defined Exception Codes ...............................................................................228
Table 5-85. Character Transfer Time vs Baud Rate .............................................................................................231
Table 5-86. TPU2000/TPU2000R Modbus CommandThroughput (Average time in mS) ....................................232
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