ABB TPU2000 Technical Manual page 116

TPU2000/2000R Modbus/Modbus Plus/ Modbus TCP/IP Automation Guide
Address
Bit 6 = PCTA
Bit 5 = PUA
Bit 4 = 63
Bit 3 =THRUFA
Bit 2 = TFCA (Note 1)
Bit 1 = TFKA (Note 1)
Bit 0 =TFSCA (Note 1)
41156 Logical Output
Bit 15 = DTC (Note 1)
Bit 14 = OCTC
Bit 13 =PDA
Bit 12 = NDA
Bit 11 = PRIM
Bit 10 = ALT1
Bit 9 = ALT2
Bit 8 = STCA (L)
Bit 7 = 87T (L)
Bit 6 = 87H (L)
Bit 5 = 2HROA (L)
Bit 4 = 5HROA (L)
Bit 3 = AHROA (L)
Bit 2 = 50P-1D (L)
Bit 1 = 50P-2D (L)
Bit 0 = 50N-1D (L)
41157 Logical Output
Bit 15 = 150P-1 (L)
Bit 14 = 50-P2 (L)
Bit 13 = 150P-2 (L)
Bit 12 = 51N-1 (L)
Bit 11 = 51N-2 (L) (Note 3)
Bit 10 = 50N-1 (L)
Bit 9 = 150N-1 (L)
Bit 8 = 50N-2 (L) (Note 3)
Bit 7 = 150N-2 (L) (Note 3)
Bit 6 = 46-1 (L)
Bit 5 = 46-2 (L)
Bit 4 = 63 (L)
Bit 3 = ULO 1
Bit 2 = ULO 2
Bit 1 = ULO 3
Bit 0 = ULO 4
41158 Logical Output
Bit 15 = ULO 5
Bit 14 = ULO 6
Bit 13 = ULO 7
Bit 12 = ULO 8
Bit 11 = ULO 9
Item
Phase C Target Alarm
Pick Up Alarm
Sudden Pressure Alarm
Through Fault Alarm
Through Fault Counter Alarm
Through Fault Counter Alarm
Through Fault Cycle Summation Alarm (lsb rightmost bit)
Unsigned Integer 16 Bit
Differential Trip Counter Alarm (msb leftmost bit)
Overcurrent Trip Counter Alarm
Phase Demand Counter Alarm
Neutral Demand Current Alarm
Primary Settings Enabled Alarm
Alternate 1 Settings Enabled Alarm
Alternate 2 Setting Enabled Alarm
Settings Table Changed Alarm Latched
Harmonic Restrained % Differential Trip Alarm Latched
Unrestrained High Set Instantaneous Differential Trip Alarm
Latched
nd
2
th
5
All Harmonics Restraint Alarm Latched
st
1
Latched
nd
2
Latched
st
1
Latched (lsb rightmost bit)
Unsigned Integer 16 Bit (msb leftmost bit)
nd
2
Latched
st
1
Latched
nd
2
Latched
Winding 1 Neutral Time Overcurrent Trip Alarm Latched
Winding 2 Neutral Time Overcurrent Seal In Alarm Latched
1stWinding 1 Neutral Instantaneous Overcurrent Seal In Alarm
Latched
nd
2
Latched
st
1
Latched
nd
2
Latched
Winding 1 Negative Sequence Time Overcurrent Seal In Alarm
Winding 2 Negative Sequence Time Overcurrent Seal In Alarm
Sudden Pressure Seal In Alarm
User Logical Output 1 Energized
User Logical Output 2 Energized
User Logical Output 3 Energized
User Logical Output 4 Energized (lsb rightmost bit)
Unsigned Integer 16 Bit
User Logical Output 5 Energized (msb leftmost)
User Logical Output 6 Energized
User Logical Output 7 Energized
User Logical Output 8 Energized
User Logical Output 9 Energized
Harmonic Restraint Alarm Latched
Harmonic Restraint Alarm Latched
Winding Phase 1 Instantaneous Overcurrent Trip Alarm
Winding 1 Phase Instantaneous Overcurrent Trip Alarm
Winding Phase 2 Instantaneous Overcurrent Trip Alarm
Winding 1 Phase Instantaneous Overcurrent Trip Alarm
Winding Phase 2 Instantaneous Overcurrent Trip Alarm
Winding 2 Phase Instantaneous Overcurrent Trip Alarm
Winding 1 Neutral Instantaneous Overcurrent Seal In Alarm
Winding 2 Neutral Instantaneous Overcurrent Seal In Alarm
Winding 2 Neutral Instantaneous Overcurrent Seal In Alarm
Description
106