ABB TPU2000 Technical Manual page 292

TPU2000/2000R Modbus/Modbus Plus/ Modbus TCP/IP Automation Guide
4.6 Transmit Programmable Output AND/OR Select ( 3 4 6 )
Bit = 0, Selected inputs are ORed together.
Bit = 1, Selected inputs are ANDed together.
Index byte is the offset into the TPU's logical output structure.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Index
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Logical Output
not used, reserved for fixed DIFF TRIP
Contact OUT5
Contact OUT7
Contact OUT4
Contact OUT6
Contact OUT3
Contact OUT2
Contact OUT1
spare
spare
spare
spare
spare
spare
spare
spare
Output Definition
DIFF Fixed Diff Trip, 87T or 87H
ALARM Fixed Self Check Alarm
87T Percentage Differential Trip
87H High Set Inst Diff Trip
2HROA 2nd Harm Restraint Output Alarm
5HROA 5th Harm Restraint Alarm
AHROA All Harm Restraint Alarm
TCFA Trip Circuit Failure Alarm
TFA Trip Failure Alarm
51P-1 Wdg 1 Phase Time OC Trip
51P-2 Wdg 2 Phase Time OC Trip
50P-1 1st Wdg 1 Phase Inst OC Trip
150P-1 2nd Wdg 1 Phase Inst OC Trip
50P-2 1st Wdg 2 Phase Inst OC Trip
150P-2 2nd Wdg 2 Phase Inst OC Trip
51N-1 Wdg 1 Neutral Time OC Trip
51G-2 Wdg 2 Ground Time OC Trip
50N-1 1st Wdg 1 Neutral Inst OC Trip
150N-1 2nd Wdg 1 Neutral Inst OC Trip
50G-2 1st Wdg 2 Ground Inst OC Trip
150G-2 2nd Wdg 2 Ground Inst OC Trip
46-1 Wdg 1 Neg Sequence Time OC Trip
46-2 Wdg 2 Neg Sequence Time OC Trip
87T-D Percentage Differential Disabled Alarm
87H-D High Set Inst Diff Disabled Alarm
51P-1D Wdg 1 Phase Time OC Disabled Alarm
51P-2D Wdg 2 Phase Time OC Disabled Alarm
51N-1D Wdg 1 Neutral Time OC Disabled Alarm
51G-2D Wdg 2 Ground Time OC Disabled Alarm
50P-1D 1st Wdg 1 Phase Inst OC Disabled Alarm
50P-2D 1st Wdg 2 Phase Inst OC Disabled Alarm
50N-1D 1st Wdg 1 Neutral Inst OC Disabled Alarm
50G-2D 1st Wdg 2 Ground Inst OC Disabled Alarm
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