Transmit Wait Register (Txpr) - Hitachi H8S/2646 Hardware Manual

15.2.5

Transmit Wait Register (TXPR)

The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a
transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
TXPR
Bit:
Initial value:
R/W:
Bit:
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9
Initial value:
R/W:
Bits 15 to 9 and 7 to 0—Transmit Wait Register: These bits set a transmit wait for the
corresponding mailboxes.
Bit x: TXPRx
0
1
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
15 14
TXPR7 TXPR6 TXPR5
0 0
R/W R/W
7 6
0 0
R/W R/W
Description
Transmit message idle state in corresponding mailbox
[Clearing condition]
Message transmission completion and cancellation completion
Transmit message transmit wait in corresponding mailbox (CAN bus
arbitration)
13 12 11
TXPR4 TXPR3
0 0
R/W R/W R/W
5 4
0 0
R/W R/W R/W
10 9
TXPR2 TXPR1
0 0 0
R/W R/W
3 2 1
0 0 0
R/W R/W
8
—
0
—
0
TXPR8
0
R/W
(Initial value)
(x = 15 to 0)
541