Pin Function Control Register (Pfcr) - Hitachi H8S/2646 Hardware Manual

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG Description
0 An interrupt is requested at the falling edge of NMI input
1 An interrupt is requested at the rising edge of NMI input
Bit 2— Reserved: Only 0 should be written to this bit.
Bit 1—Reserved: This bit is always read as 0 and cannot be modified.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled
Note: When the DTC is used, the RAME bit must not be cleared to 0.
3.2.3

Pin Function Control Register (PFCR)

Bit : 7
—
Initial value : 0
R/W : R/W
PFCR is an 8-bit readable-writeable register that performs address output control in extension
modes involving ROM.
PFCR is initialized to H'0D/H'00 by a reset and in the hardware standby mode.
Bits 7 to 4— Reserved: Only 0 should be written to these bits.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.
82
6 5
— — —
0 0
R/W R/W R/W
4 3 2
AE3 AE2
0 1/0 1/0
R/W R/W
(Initial value)
(Initial value)
1 0
AE1 AE0
0 1/0
R/W R/W