12.2
Register Descriptions
12.2.1
Timer Counter (TCNT)
Bit
:
7
Initial value :
0
R/W
:
R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), an internal reset, a NMI interrupt (only WDT1), or an interval timer interrupt
(WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see
section 12.2.4, Notes on Register Access.
12.2.2
Timer Control/Status Register (TCSR)
TCSR0
Bit
:
7
OVF
Initial value :
0
R/W
:
R/(W)*
Note: * Only a 0 may be written to this bit to clear the flag.
TCSR1
Bit
:
7
OVF
Initial value :
0
R/W
:
R/(W)*
Note: * Only a 0 may be written to this bit to clear the flag.
6
5
0
0
R/W
R/W
6
5
WT/IT
TME
0
0
R/W
R/W
6
5
WT/IT
TME
0
0
R/W
R/W
4
3
0
0
R/W
R/W
R/W
4
3
—
—
CKS2
1
1
—
—
R/W
4
3
PSS
RST/NMI
CKS2
0
0
R/W
R/W
R/W
2
1
0
0
0
0
R/W
R/W
2
1
0
CKS1
CKS0
0
0
0
R/W
R/W
2
1
0
CKS1
CKS0
0
0
0
R/W
R/W
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