Hitachi H8S/2646 Hardware Manual page 726

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Example in which Flash Memory Block Area EB0 is Overlapped

1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the

area (EB0) for which real-time programming is required.

2. Real-time programming is performed using the overlapping RAM.

3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.

4. The data written in the overlapping RAM is written into the flash memory space (EB0).

Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks

regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting

the P or E bit in flash memory control register 1 (FLMCR1), will not cause a transition

to program mode or erase mode. When actually programming or erasing a flash

memory area, the RAMS bit should be cleared to 0.

2. A RAM area cannot be erased by execution of software in accordance with the erase

algorithm while flash memory emulation in RAM is being used.

3. Block area EB0 contains the vector table. When performing RAM emulation, the

vector table is needed in the overlap RAM.

Flash memory

Figure 20-15 Example of RAM Overlap Operation

This area can be accessed

from both the RAM area

and flash memory area