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IRR—Interrupt Register
Bit
15
IRR7
Initial value
0
Read/Write
R/(W)*
Bus Off Interrupt Flag
0
[Clearing condition]
Writing 1
Bus off state caused by transmit error
1
[Setting condition]
When TEC ≥ 256
Overload Frame Interrupt Flag
0
[Clearing condition]
Writing 1
1
Overload frame transmission
[Setting conditions]
When overload frame is transmitted
Note: * Only 1 can be written, to clear the flag.
14
13
IRR6
IRR5
IRR4
0
0
R/(W)*
R/(W)*
R/(W)*
Remote Frame Request Interrupt Flag
0
[Clearing condition]
Clearing of all bits in RFPR (remote request wait register) in the mailbox,
which enables the receive interrupt requests in MBIMR
1
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed, when corresponding MBIMR = 0
Transmit Overload Warning Interrupt Flag
0
[Clearing condition]
Writing 1
1
Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
Receive Overload Warning Interrupt Flag
0
[Clearing condition]
Writing 1
1
Error warning state caused by receive error
[Setting condition]
When REC ≥ 96
Error Passive Interrupt Flag
0
[Clearing condition]
Writing 1
1
Error passive state caused by transmit/receive error
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
H'F812
12
11
10
IRR3
IRR2
0
0
0
R/(W)*
R/(W)*
Reset Interrupt Flag
0
[Clearing condition]
Writing 1
1
Transition to hardware reset (HCAN module stop, software
standby)
[Setting condition]
When reset processing is completed after hardware reset
transition (HCAN module stop, software standby)
Note: After canceling a reset or returning from hardware standby
mode, the module stop bit is initialized yo 1. HCAN then
enters a module-stopped state.
Receive Message Interrupt Flag
0
[Clearing condition]
Clearing of all bits in RXPR (receive complete register) in the mailbox,
which enables the receive interrupt requests in MBIMR
1
Data frame or remote frame received and stored in mailbox
[Setting conditions]
When data frame or remote frame reception is completed, when
corresponding MBIMR = 0
HCAN
9
8
IRR1
IRR0
0
1
R/(W)*
R/(W)*
885
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