System Clock Control Register (Sckcr) - Hitachi H8S/2646 Hardware Manual

22.2.2

System Clock Control Register (SCKCR)

Bit :
PSTOP
Initial value :
R/W : R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls ø output. See section 22.12, ø Clock Output Disable Function, for details.
Bit 7
High Speed Mode,
Medium Speed Mode,
Sub-Active Mode
PSTOP
0 ø output (initial value)
1 Fixed high
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid after transition to software standby mode, watch
mode, or sub-active mode
1 Specified multiplication factor is valid immediately after STC bits are rewritten
732
7 6 5
— —
0 0 0
— —
Sleep Mode,
Sub-Sleep Mode
ø output
Fixed high
4 3
— STCS SCK2
0 0
— R/W
Description
Software Standby
Mode, Watch Mode,
and Direct Transition
Fixed high
Fixed high
2 1
SCK1 SCK0
0 0
R/W R/W R/W
Hardware
Standby Mode
High impedance
High impedance
(Initial value)
0
0