Block Diagram - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Block Diagram

Figure 8-1 shows a block diagram of the DTC.

The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to

the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register

information.

Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.

Interrupt controller

CPU interrupt

DTCERA to DTCERG, I

: DTC mode registers A and B

: DTC transfer count registers A and B

: DTC source address register

: DTC destination address register

: DTC enable registers A to G, I

: DTC vector register

Figure 8-1 Block Diagram of DTC

Internal address bus

Internal data bus