Hitachi H8S/2646 Hardware Manual page 82

Type Instruction
Arithmetic DIVXS
operations
CMP
NEG
EXTU
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
50
*1
Size Function
Rd ÷ Rs → Rd
B/W
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
0 – Rd → Rd
B/W/L
Takes the two's complement (arithmetic complement) of
data in a general register.
Rd (zero extension) → Rd
W/L
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
Rd (sign extension) → Rd
W/L
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
@ERd – 0, 1 → (<bit 7> of @ERd)
B
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
(EAs) × (EAd) + MAC → MAC
—
Performs signed multiplication on memory contents and
adds the result to the multiply-accumulate register. The
following operations can be performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
0 → MAC
—
Clears the multiply-accumulate register to zero.
Rs → MAC, MAC → Rd
L
Transfers data between a general register and a
multiply-accumulate register.
*2