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Hardware reset
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)
GSR3 = 1 (automatic)
Initialization of HCAN module
Clear IRR0
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method initialization
MCR0 = 0
GSR3 = 0?
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
GSR3 = 0 & 11
recessive bits received?
CAN bus communication enabled
Notes: *1 When IRR0 is set to 1 (automatically) due to a hardware reset
initiated reset processing" interrupt is generated.
*2 In a reset and in hardware standby mode, the module stop bit is initialized to 1 and
the HCAN enters the module stop state.
*1
No
Yes
No
Yes
Figure 15-4 Hardware Reset Flowchart
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
: Settings by user
: Processing by hardware
*2
, a "hardware reset
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