Hitachi H8S/2646 Hardware Manual page 351

Bit 3 Bit 2
Channel IOC3 IOC2
0 0 0
1
1 0
1
Note: *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 1 Bit 0
IOC1 IOC0 Description
0 0 TGR0C is Output disabled
output
1
compare
0 register
1
1
0 0
1
1 0
1
0 0 TGR0C is
input
1
capture
*
1
register
* *
Initial output is 0
output
* 1
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC0 pin
* 1
Capture input
source is channel
1/count clock
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1
count-up/count-down
*: Don't care
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