ø
Address bus
AS
RD
HWR, LWR
Data bus
Figure 2-23 Pin States in On-Chip HCAN Module Access
2.9.5
External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 7, Bus Controller.
2.10
Usage Note
2.10.1
TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or
ER5 is used.
2.10.2
Caution to observe when using bit manipulation instructions
The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte, then, after bit
manipulation, they write data in a unit of byte. Therefore, caution must be exercised when
executing any of these instructions for registers and ports that include write-only bits.
76
Bus cycle
T2
T1
Held
High
High
High
High-impedance state
T3
T4