21.1.2
Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 21-1 shows the register
configuration.
Table 21-1 Clock Pulse Generator Register
Name
System clock control register
Low-power control register
Note:* Lower 16 bits of the address.
21.2
Register Descriptions
21.2.1
System Clock Control Register (SCKCR)
Bit
:
7
PSTOP
Initial value
:
0
R/W
:
R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control, selection of operation when the PLL circuit frequency multiplication factor is
changed, and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
High Speed Mode,
Medium Speed Mode,
Sub-Active Mode
PSTOP
0
ø output (initial value)
1
Fixed high
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
716
Abbreviation
SCKCR
LPWRCR
6
5
4
—
—
—
0
0
0
—
—
—
Description
Sleep Mode,
Sub-Sleep Mode
ø output
Fixed high
R/W
Initial Value
R/W
H'00
R/W
H'00
3
2
STCS
SCK2
0
0
R/W
R/W
Software Standby
Mode, Watch Mode,
and Direct Transition
Fixed high
Fixed high
Address*
H'FDE6
H'FDEC
1
0
SCK1
SCK0
0
0
R/W
R/W
Hardware
Standby Mode
High impedance
High impedance