Pwm Channel 2 Operation - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Stopping: When the CST bit in PWCR1 is cleared to 0, PWCNT1 is reset and stops. All PWM

outputs go low (or high if the corresponding bit in PWPR1 is set to 1).

PWM Channel 2 Operation

PWM waveforms are output from pins PWM2A to PWM2H as shown in figure 17-11.

Initial Settings: Set the PWM output polarity in PWPR2; enable the pins for PWM output with

PWOCR2; select the clock to be input to PWCNT2 with bits CKS2 to CKS0 in PWCR2; set the

PWM conversion cycle in PWCYR2; and set the first frame of data in PWBFR2A, PWBFR2B,

PWBFR2C, and PWBFR2D.

Activation: When the CST bit in PWCR2 is set to 1, a compare match between PWCNT2 and

PWCYR2 is generated. Data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from

PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and

from PWBFR2D to PWDTR2D or PWDTR2H, according to the value of the TDS bit. PWCNT2

starts counting up. At the same time the CMF bit in PWCR2 is set, so that, if the IE bit in PWCR2

has been set, an interrupt can be requested or the DTC can be activated.

Waveform Output: The PWM outputs go high when a compare match occurs between PWCNT2

and PWCYR2. When a compare match occurs between PWCNT2 and PWDTR2A-H, the

corresponding PWM output goes low. If the corresponding bit in PWPR2 is set to 1, the output is

TDS (PWBFR2A) = 0

Next Frame: When a compare match occurs between PWCNT2 and PWCYR2, data is transferred

from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F,

from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or

PWDTR2H, according to the value of the TDS bit. PWCNT2 is reset and starts counting up from

TDS (PWBFR2A) = 1

Figure 17-11 PWM Channel 2 Operation

TDS (PWBFR2A) = 0