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5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operating mode
including the standby mode.
• Main system clock f
• Subsystem clock f
XT
• CPU clock f
CPU
• Clock to peripheral hardware
The function and operation of the clock generator are determined by the processor clock control register (PCC)
as follows.
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (6.4 µ s when operated
at 5.0 MHz) is selected (PCC = 04H). Main system clock oscillation stops while a low level is applied to the
RESET pin.
(b) With the main system clock selected, one of the five stages of minimum instruction execution time (0.4 µ s, 0.8
µ s, 1.6 µ s, 3.2 µ s, and 6.4 µ s: when operated at 5.0 MHz) can be selected by setting PCC.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. When
the system is not using the subsystem clock, the power consumption in the STOP mode can be decreased if
the internal feedback resistor is not used by setting bit 6 (FRC) of PCC.
(d) PCC can be used to select the subsystem clock and to operate the system with low power consumption (122
µ s when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped using PCC. The HALT mode
can be used, but the STOP mode cannot be used (subsystem clock oscillation cannot be stopped).
(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied
to the watch timer and clock output functions only. Thus, the watch function and the clock output function can
also be continued in the standby state. However, since all other peripheral hardware operate with the main
system clock, the peripheral hardware also stop if the main system clock is stopped (except during operation
using an externally input clock).
114
CHAPTER 5 CLOCK GENERATOR
X
User's Manual U11302EJ4V0UM
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