Format Of Timer Clock Select Register 2 - NEC mPD780208 Subseries User Manual

8-bit single-chip microcontrollers
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Symbol
7
6
5
TCL2
TCL27
TCL26
TCL25
Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting
TCL2 (stopping operation is not necessary when rewriting the same data).
The operation is stopped by the following methods.
• Buzzer output: Input 0 to bit 7 (TCL27) of TCL2
• Watch timer:
2. Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation
has started is prohibited.
Remarks 1. f
X
2. f
XT
3. x: don't care
4. Figures in parentheses apply to operation with f
188
CHAPTER 11 BUZZER OUTPUT CONTROLLER
Figure 11-2. Format of Timer Clock Select Register 2
4
3
2
1
TCL24
0
TCL22
TCL21
Input 0 to bit 2 (TMC22) of the watch timer mode control register
(TMC2)
: Main system clock oscillation frequency
: Subsystem clock oscillation frequency
User's Manual U11302EJ4V0UM
0
Address
After reset
TCL20
FF42H
00H
TCL22
TCL21
TCL20
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TCL24 Watch timer count clock selection
8
f
/2
(19.5 kHz)
0
X
1
f
(32.768 kHz)
XT
TCL27
TCL26
TCL25
0
x
x
1
0
0
1
0
1
1
1
0
1
1
1
= 5.0 MHz or f
X
R/W
R/W
Count clock selection
Watchdog timer mode
Interval timer mode
3
4
f
/2
(625 kHz)
f
/2
(313 kHz)
X
X
4
5
f
/2
(313 kHz)
f
/2
(156 kHz)
X
X
5
6
f
/2
(156 kHz)
f
/2
(78.1 kHz)
X
X
6
7
f
/2
(78.1 kHz)
f
/2
(39.1 kHz)
X
X
7
8
f
/2
(39.1 kHz)
f
/2
(19.5 kHz)
X
X
8
9
f
/2
(19.5 kHz)
f
/2
(9.8 kHz)
X
X
9
10
f
/2
(9.8 kHz)
f
/2
(4.9 kHz)
X
X
11
12
f
/2
(2.4 kHz)
f
/2
(1.2 kHz)
X
X
Buzzer output frequency selection
Buzzer output disabled
10
f
/2
(4.9 kHz)
X
11
f
/2
(2.4 kHz)
X
12
f
/2
(1.2 kHz)
X
Setting prohibited
= 32.768 kHz.
XT

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