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Symbol
<7>
<6>
<5>
PCC
MCC
FRC
CLS
Notes 1. Bit 5 is a read-only bit.
2. This bit can be set to 1 only when the subsystem clock is not used.
3. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system
clock oscillation. The STOP instruction should not be used.
Cautions 1. Bit 3 must be set to 0.
2. Do not set MCC while an external clock is being input. This is because the X2 pin is pulled
up to V
Remarks 1. f
: Main system clock oscillation frequency
X
2. f
: Subsystem clock oscillation frequency
XT
CHAPTER 5 CLOCK GENERATOR
Figure 5-3. Format of Processor Clock Control Register
<4>
3
2
1
CSS
0
PCC2
PCC1
.
DD
User's Manual U11302EJ4V0UM
0
Address
After reset
PCC0
FFFBH
04H
R/W
CSS
PCC2
PCC1
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
1
1
0
Other than above
R
CLS
CPU clock status
0
Main system clock
Subsystem clock
1
R/W
FRC
Subsystem clock feedback resistor selection
0
Internal feedback resistor used
1
Internal feedback resistor not used
R/W
Main system clock oscillation control
MCC
0
Oscillation possible
1
Oscillation stopped
R/W
Note 1
R/W
CPU clock (f
) selection
PCC0
CPU
f
0
X
1
f
/2
X
2
0
f
/2
X
3
1
f
/2
X
4
f
/2
0
X
f
/2
0
XT
1
0
1
0
Setting prohibited
Note 2
Note 3
103
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