System Configuration With Busy Control Option - NEC mPD780208 Subseries User Manual

8-bit single-chip microcontrollers
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(4) Synchronization control
Busy control and strobe control are used to synchronize transmission/reception data between the master
device and slave device.
By using these functions, a bit slippage in data being transmitted/received can be detected.
(a) Busy control option
Busy control is used to allow a slave device to output a busy signal to the master device, so that the
master device puts serial transmission/reception into a wait state while the busy signal is active.
To use the busy control option, the following conditions must be satisfied.
• Set bit 5 (ATE) of serial operating mode register 1 (CSIM1) to 1.
• Set bit 1 (BUSY1) of the automatic data transmit/receive control register (ADTC) to 1.
Figure 14-18 shows the system configuration of the master device and a slave device when the busy
control option is used.
Figure 14-18. System Configuration with Busy Control Option
The master device inputs the busy signal output by the slave device to the BUSY/P24 pin. It samples
the input busy signal in synchronization with the fall of the serial clock. Even if the busy signal
becomes active while 8-bit data is being transmitted or received, transmission/reception is not put
into a wait state. If the busy signal is active at the rising edge of the serial clock two clocks after
transmission or reception of 8-bit data has been completed, the busy signal becomes valid. After
that, transmission or reception is put into a wait state while the busy signal is active.
The active level of the busy signal is specified by bit 0 (BUSY0) of ADTC, as follows.
BUSY0 = 0: Active high
BUSY0 = 1: Active low
When using the busy control option, select the internal clock as the serial clock. Busy control cannot
be executed with an external clock.
Figure 14-19 shows the operation timing when using the busy control option.
Caution
Busy control cannot be executed when the interval time is controlled by using the
automatic data transmit/receive interval specification register (ADTI). If an attempt
is made to execute both control operations at the same time, busy control is invalid.
292
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
Master device
µ
( PD780208 Subseries)
SCK1
SO1
SI1
BUSY
User's Manual U11302EJ4V0UM
Slave device
SCK1
SO1
SI1

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