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Symbol
<7>
<6>
5
ADM
CS
TRG
FR1
ADM3 ADM2 ADM1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
A/D conversion time selection
FR1
FR0
When operated at f
0
0
160/f
0
1
80/f
1
0
200/f
1
1
Setting prohibited
TRG
External trigger selection
0
No external trigger (software start mode)
1
Conversion started by external trigger (hardware start mode)
CS
A/D conversion operation control
0
Operation stop
1
Operation start
Notes 1. Set so that the A/D conversion time is 19.1 µ s or more.
2. Setting prohibited because the A/D conversion time is less than 19.1 µ s.
Cautions 1. Bit 0 must be set to 1.
2. In order to reduce the power consumption of the A/D converter when the standby
function is working, clear bit 7 (CS) of this register to 0 to stop the A/D conversion
operation before executing the HALT or STOP instruction.
3. When restarting a stopped A/D conversion operation, start the A/D conversion
operation after clearing the interrupt request flag (ADIF) to 0.
Remark f
: Main system clock oscillation frequency
X
CHAPTER 12 A/D CONVERTER
Figure 12-2. Format of A/D Converter Mode Register
4
3
2
1
FR0 ADM3 ADM2 ADM1
Analog input channel selection
0
ANI0
1
ANI1
0
ANI2
1
ANI3
0
ANI4
1
ANI5
0
ANI6
1
ANI7
= 5.0 MHz
X
(32.0 µ s)
X
Note 2
(setting prohibited
)
X
(40.0 µ s)
X
User's Manual U11302EJ4V0UM
0
Address After reset
1
FF80H
01H
Note 1
When operated at f
(38.1 µ s)
160/f
X
(19.1 µ s)
80/f
X
(47.7 µ s)
200/f
X
R/W
R/W
= 4.19 MHz
X
195
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