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(1) Interrupt request flag registers (IF0L, IF0H)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET.
IF0L and IF0H are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as
a 16-bit register IF0, use a 16-bit memory manipulation instruction for setting.
RESET input clears these registers to 00H.
Symbol
<7>
<6>
<5>
IF0L
TMIF3
CSIIF1
CSIIF0
7
6
<5>
Note
IF0H
0
0
WTIF
Note
WTIF is the test input flag. A vectored interrupt request is not generated.
Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer.
If the watchdog timer is used in watchdog timer mode 1, set the TMIF4 flag to 0.
2. Always set bits 6 and 7 of IF0H to 0.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared,
and then servicing of the interrupt routine is started.
4. When the interrupt request flag register is manipulated (including by a 1-bit memory
manipulation instruction), if an interrupt request corresponding to another flag in the
same register is generated, the flag corresponding to that interrupt request may not be
set to 1.
340
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
Figure 16-2. Format of Interrupt Request Flag Register
<1>
<4>
<3>
<2>
PIF3
PIF2
PIF1
PIF0
<4>
<3>
<2>
<1>
KSIF
ADIF TMIF2
TMIF1
User's Manual U11302EJ4V0UM
<0>
Address
After reset
TMIF4
FFE0H
00H
<0>
TMIF0
FFE1H
00H
xxIF
Interrupt request flag
0
No interrupt request signal
1
Interrupt request signal is generated: Interrupt request state
R/W
R/W
R/W
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