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(5) Sampling clock select register (SCS)
This register is used to set the clock used to sample the valid edge input to INTP0. When remote controlled
data reception is carried out using INTP0, digital noise is eliminated using the sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS to 00H.
Symbol
7
6
5
SCS
0
0
0
N + 1
Caution f
/2
X
peripheral hardware. f
Remarks 1. N: Value (N = 0 to 4) of bits 0 to 2 (PCC0 to PCC2) of processor clock control register (PCC)
2. f
: Main system clock oscillation frequency
X
3. Figures in parentheses apply to operation with f
344
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
Figure 16-6. Format of Sampling Clock Select Register
4
3
2
1
0
0
0
SCS1 SCS0
is the clock supplied to the CPU, f
N + 1
/2
stops in the HALT mode.
X
User's Manual U11302EJ4V0UM
0
Address
After reset
FF47H
00H
SCS1
SCS0
INTP0 sampling clock selection
0
0
f
/2
N + 1
X
0
1
Setting prohibited
1
0
f
/2
6
(78.1 kHz)
X
1
1
f
/2
7
(39.1 kHz)
X
6
7
/2
and f
/2
are the clocks supplied to the
X
X
= 5.0 MHz.
X
R/W
R/W
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