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FRC
XT1/P04
Subsystem
clock oscillator
XT2
f
/8
X
f
/16
X
X1
Main system
clock oscillator
X2
STOP
Notes 1. Bit 6 of display mode register 0 (DSPM0)
2. Bits 4 to 7 of display mode register 1 (DSPM1)
CHAPTER 5 CLOCK GENERATOR
Figure 5-1. Clock Generator Block Diagram
f
XT
Noise
eliminator
DIGS0 to
DIGS3
Note 1
DSPM06
f
X
Watchdog timer
Prescaler
f
f
f
f
X
X
X
X
2
3
2
2
2
MCC
User's Manual U11302EJ4V0UM
Clock output function
Watch timer
Note 2
1/2
Prescaler
f
XT
2
f
X
4
2
Standby
controller
3
FRC
CLS
CSS PCC2 PCC1 PCC0
Processor clock control register
Internal bus
Clock to
peripheral
hardware
CPU clock
(f
)
CPU
To INTP0
sampling
clock
101
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