Calculating Total Power Dissipation; Segment Type (Display Mode 1: Dspm05 = 0) - NEC mPD780208 Subseries User Manual

15.10 Calculating Total Power Dissipation

The total power dissipation of the µ PD780208 Subseries is the sum of the values of the following three
parts. Design your application set so that the sum is lower than the total power dissipation P
in Figure 15-22. (The recommended operating condition is 80% or lower of the rated value.)
<1> CPU: The power consumed by the CPU and calculated with V
<2> Output pins: The power dissipation when the maximum current flows through the display output pins
<3> Pull-down resistors: The power consumed at the on-chip pull-down resistors connected to the display output
Figure 15-22. Allowable Total Power Dissipation P
800
600
400
200
The following example assumes the case where the display examples shown in 15.9 are displayed.

15.10.1 Segment type (display mode 1: DSPM05 = 0)

The calculation method for the total power dissipation in the case of the display example in Figure 15-23 is
described below.
Example Assume the following conditions:
= 5 V ±10%, 5.0 MHz oscillation
V
DD
Supply current (I
Display output: 11 grids × 10 segments (cut width = 1/16: when DIMS1 to DIMS3 = 000B)
Display output voltage: grid
Fluorescent display control voltage (V
Mask option pull-down resistor = 25 kΩ
326
CHAPTER 15 VFD CONTROLLER/DRIVER
pins
–40
0
Temperature [°C ]
) = 21.6 mA
DD
Maximum current at the grid pin is 15 mA.
Maximum current at the segment pin is 3 mA.
At the key scan timing, display output pin is OFF.
V = V
OD
segments V = V
OD
LOAD
User's Manual U11302EJ4V0UM
(max.) x I
DD
(T = –40 to +85
T A
+80
+40
– 2 V (voltage drop of 2 V)
DD
– 0.4 V (voltage drop of 0.4 V)
DD
) = –35 V
stipulated
T
(max.)
DD
°
C)