NEC 78014Y Series User Manual

8-bit single-chip microcontrollers

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User's Manual

µ PD78014, 78014Y SUBSERIES

8-BIT SINGLE-CHIP MICROCONTROLLERS

µ PD78011B

www.DataSheet4U.com

µ PD78012B

µ PD78013

µ PD78014

µ PD78P014

µ PD78011B (A)

µ PD78012B (A)

µ PD78013 (A)

µ PD78014 (A)

Document No.

Date Published

Printed in Japan

µ PD78011BY

µ PD78012BY

µ PD78013Y

µ PD78014Y

µ PD78P014Y

U10085EJ7V0UM00 (7th edition)

October 1997 N

1992

Table of Contents

Summary of Contents for NEC 78014Y Series

Page 1 User’s Manual µ PD78014, 78014Y SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLERS µ PD78011B µ PD78011BY www.DataSheet4U.com µ PD78012B µ PD78012BY µ PD78013 µ PD78013Y µ PD78014 µ PD78014Y µ PD78P014 µ PD78P014Y µ PD78011B (A) µ PD78012B (A) µ PD78013 (A) µ PD78014 (A) Document No.
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Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Page 6 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 Main Revisions in This Edition Pages Description p. 43, 44, 56, 57 The following subseries were added in sections 1.6 and 2.6, “78K/0 Series Expansion.” µ PD78075B, 78075BY, 780018, 780018Y, 780058, 780058Y, 780034, 780034Y, 780024, 780024Y, 78014H, 780964, 780924, 780228, 78044H, 78044F, 78098B, 780973 Subseries p.
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Page 9 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78014, 78014Y Subseries and design and develop its application systems and programs. Target subseries are as follows. • µ PD78014 Subseries : µ PD78011B, 78012B, 78013, 78014, 78P014 µ...
Page 10 To confirm the details of the register whose register name is known: → Refer to APPENDIX D REGISTER INDEX. For the details of the µ PD78014, 78014Y Subseries instruction function: → Refer to the 78K/0 SERIES USER’S MANUAL, Instructions. (IEU1372). For the electrical specifications of the µ...
Page 11 This manual describes points for which functions of µ PD78014 and µ PD78014Y Subseries Chapter composition are not same in different chapters. The chapters explaining the subseries are shown in the table below. If you use one of the subseries, you should read the chapters with √ marks. µ...
Page 12 IC-8874 IC-3411 µ PD78011BY, 78012BY, 78013Y, 78014Y Data Sheet IC-8573 IC-3405 µ PD78P014Y Data Sheet IC-8572 IC-3180 µ PD78014, 78014Y Series Special Function Register Table IEM-5527 — 78K/0 Series User’s Manual — Instruction U12326J IEU-1372 78K/0 Series Instruction Set U10903J —...
Page 13 • Document related to development tools (User’s Manual) Document Document name Number Japanese Version English Version RA78K Series Assembler Package Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 RA78K Series Structured Assembler Preprocessor U12323J EEU-1402 RA78K0 Assembler Package Operation U11802J U11802E Assembly Language U11801J U11801E Structured Assembly Language...
Page 14 C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade of NEC Semiconductor Devices C11531J C11531E Reliability and Quality Control of NEC Semiconductor Devices C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance of Semiconductor Devices C11893J...
Page 15: Table Of Contents
CONTENTS OUTLINE ( µ PD78014 Subseries)................. CHAPTER 1 Features .......................... Application Fields ......................Ordering Information ..................... Quality Grade ......................... Pin Configurations (Top View) ..................78K/0 Series Expansion ....................Block Diagram ........................ Outline of Function ......................Differences among µ PD78011B, 78012B, 78013, 78014 and µ PD78011B(A), 78012B(A), 78013(A), 78014(A) ..................
Page 16 3.2.14 V ............................3.2.15 V ............................( µ PD78P014 only) ....................... 3.2.16 V 3.2.17 IC (Mask ROM version only) ..................... Input/Output Circuit and Recommended Connection of Unused Pins ....PIN FUNCTION ( µ PD78014Y Subseries) ............CHAPTER 4 Pin Function List ......................4.1.1 Normal operating mode pins .....................
Page 17 Operand Address Addressing ..................115 5.4.1 Data memory addressing ....................115 5.4.2 Implied addressing ......................120 5.4.3 Register addressing ......................121 5.4.4 Direct addressing ....................... 122 5.4.5 Short direct addressing ...................... 123 5.4.6 Special function register (SFR) addressing ..............125 5.4.7 Register indirect addressing ....................
Page 18 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ................ 171 Outline of On-chip Timer in µ PD78014, 78014Y Subseries ........171 16-Bit Timer/Event Counter Functions ............... 172 16-Bit Timer/Event Counter Configuration ..............173 16-Bit Timer/Event Counter Control Registers ............178 16-Bit Timer/Event Counter Operations ..............186 8.5.1 Interval timer operations ....................
Page 19 12.3 Clock Output Function Control Registers ..............240 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .............. 243 13.1 Buzzer Output Control Circuit Functions ..............243 13.2 Buzzer Output Control Circuit Configuration ............243 13.3 Buzzer Output Function Control Registers ............... 244 CHAPTER 14 A/D CONVERTER ....................
Page 20 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 ............... 409 17.1 Serial Interface Channel 1 Functions ................. 409 17.2 Serial Interface Channel 1 Configuration ..............410 17.3 Serial Interface Channel 1 Control Registers ............413 17.4 Serial Interface Channel 1 Operations ............... 418 17.4.1 Operation stop mode ......................
Page 21 22.2 PROM Programming ...................... 497 22.2.1 Operating modes ........................ 497 22.2.2 PROM write procedure ....................... 498 22.2.3 PROM read procedure ....................... 500 22.3 Erasure Characteristics (for µ PD78P014DW, 78P014YDW) ........501 22.4 Opaque Film on Erasure Window (for µ PD78P014DW, 78P014YDW) ....501 22.5 Screening of One-Time PROM Versions ..............
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Page 23 LIST OF FIGURES (1/7) Figure No. Title, Page Pin Input/Output Circuit List ......................Pin Input/Output Circuit List ......................Memory Map ( µ PD78011B, 78011BY) ..................... Memory Map ( µ PD78012B, 78012BY) ..................... Memory Map ( µ PD78013, 78013Y) ....................Memory Map ( µ PD78014, 78014Y) ....................Memory Map ( µ...
Page 24 LIST OF FIGURES (2/7) Figure No. Title, Page External Circuit of Main System Clock Oscillator ................160 External Circuit of Subsystem Clock Oscillator ................. 160 Examples of Resonator with Bad Connection ................... 161 Main System Clock Stop Function ....................165 System Clock and CPU Clock Switching ..................
Page 25 LIST OF FIGURES (3/7) Figure No. Title, Page 9-13 Square-Wave Output Operation Timings ..................219 9-14 8-Bit Timer Register Start Timings ....................220 9-15 External Event Counter Operation Timings ..................220 9-16 Timings after Compare Register Change during Timer Count Operation ......... 221 10-1 Watch Timer Block Diagram ......................
Page 26 LIST OF FIGURES (4/7) Figure No. Title, Page 15-11 Example of Serial Bus Configuration with SBI .................. 284 15-12 SBI Transfer Timings ........................286 15-13 Bus Release Signal ........................... 287 15-14 Command Signal ..........................287 15-15 Address ............................. 288 15-16 Slave Selection with Address ......................288 15-17 Command ............................
Page 27 LIST OF FIGURES (5/7) Figure No. Title, Page 16-19 Data ..............................350 16-20 Acknowledge Signal .......................... 351 16-21 Busy Signal, Ready Signal ........................ 352 16-22 RELT, CMDT, RELD and CMDD Operations (Master) ..............357 16-23 RELD and CMDD Operations (Slave) ....................357 16-24 ACKT Operation ..........................
Page 28 LIST OF FIGURES (6/7) Figure No. Title, Page 17-10 Basic Transmit Mode Operation Timings ..................430 17-11 Basic Transmit Mode Flowchart ......................431 17-12 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........432 17-13 Repeat Transmit Mode Operation Timings ..................434 17-14 Repeat Transmit Mode Flowchart .....................
Page 29 LIST OF FIGURES (7/7) Figure No. Title, Page 20-1 Oscillation Stabilization Time Select Register Format ..............484 20-2 HALT Mode Clear upon Interrupt Request Generation ..............486 20-3 HALT Mode Clear upon RESET Input ....................487 20-4 STOP Mode Clear upon Interrupt Request Generation ..............489 20-5 STOP Mode Clear upon RESET Input ....................
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Page 31 LIST OF TABLES (1/3) Table No. Title, Page Differences among µ PD78011B, 78012B, 78013, 78014 and µ PD78011B(A), 78012B(A), 78013(A), 78014(A) .......................... Mask Options in Mask ROM Versions ....................Mask Options in Mask ROM Versions ....................Pin Input/Output Circuit Types ......................Pin Input/Output Circuit Types ......................
Page 32 LIST OF TABLES (2/3) Table No. Title, Page 9-10 Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Tmer/Event Counter ................... 219 10-1 Interval Timer Interval Time ......................223 10-2 Watch Timer Configuration ....................... 224 10-3 Interval Timer Interval Time ......................
Page 33 LIST OF TABLES (3/3) Table No. Title, Page 20-1 HALT Mode Operating Status ......................485 20-2 Operation after HALT Mode Clear ....................487 20-3 STOP Mode Operating Status ......................488 20-4 Operation after STOP Mode Clear ....................490 21-1 Hardware Status after Reset ......................493 Differences between µ...
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Page 35: Chapter 1 Outline ( Μ Pd78014 Subseries)
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.1 Features • On-chip large-capacity ROM and RAM Item Program Memory Data Memory Part (ROM) Internal high-speed RAM Buffer RAM Number µ PD78011B 8 Kbytes 512 bytes 32 bytes µ...
Page 36: Application Fields
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.2 Application Fields For the µ PD78011B, 78012B, 78013, 78014, and 78P014 Telephone, VCR, audio system, camera, home electric appliances, etc. For the µ PD78011B(A), 78012B(A), 78013(A), and 78014(A) Automobile electronic equipment, gas detection breaker, safety equipment, etc. 1.3 Ordering Information Part Number Package...
Page 37: Quality Grade
××× is the ROM code suffix. Remark Please refer to the Quality grade on NEC Semiconductor Devices (C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 38: Pin Configurations (Top View)
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.5 Pin Configurations (Top View) (1) Normal operating mode • 64-pin plastic shrink DIP (750 mils) µ PD78011BCW-×××, 78012BCW-××× µ PD78013CW-×××, 78014CW-×××, 78P014CW µ PD78011BCW(A)-×××, 78012BCW(A)-××× µ PD78013CW(A)-×××, 78014CW(A)-××× • 64-pin ceramic shrink DIP with window (750 mils) µ...
Page 39 CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 64-pin plastic QFP (14 × 14 mm) • µ PD78011BGC-×××-AB8, 78012BGC-×××-AB8 µ PD78013GC-×××-AB8, 78014GC-×××-AB8, 78P014GC-AB8 µ PD78011BGC(A)-×××-AB8, 78012BGC(A)-×××-AB8 µ PD78013GC(A)-×××-AB8, 78014GC(A)-×××-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P30/TO0 P11/ANI1 P31/TO1...
Page 40 CHAPTER 1 OUTLINE ( µ PD78014 Subseries) A8 to A15 : Address Bus : Programmable Clock AD0 to AD7 : Address/Data Bus : Read Strobe ANI0 to ANI7 : Analog Input RESET : Reset ASTB : Address Strobe SB0, SB1 : Serial Bus : Analog Power Supply SCK0, SCK1...
Page 41 CHAPTER 1 OUTLINE ( µ PD78014 Subseries) (2) PROM programming mode • 64-pin plastic shrink DIP (750 mils) µ PD78P014CW • 64-pin ceramic shrink DIP with window (750 mils) µ PD78P014DW Open Open www.DataSheet4U.com RESET Cautions 1. (L) : Connect individually to V via a pull-down resistor.
Page 42 CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 64-pin plastic QFP (14 × 14 mm) • µ PD78P014GC-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Open Open RESET www.DataSheet4U.com 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Cautions 1.
Page 43: Series Expansion
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.6 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Mass-produced products Products under development The subseries whose names end with Y support the I C bus specifications Control µ...
Page 44 CHAPTER 1 OUTLINE ( µ PD78014 Subseries) The following table shows the differences among subseries functions. Function Timer 8-bit 10-bit 8-bit Serial Interface I/O V MIN. External Part Number Capacity 8-bit 16-bit Watch WDT Value Expansion Control µ PD78075B 32K to 40K —...
Page 45: Block Diagram
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.7 Block Diagram TO0/P30 16-bit TIMER/ EVENT COUNTER TI0/INTP0/P00 PORT0 P01 to P03 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 PORT1 P10 to P17 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 PORT2 P20 to P27 WATCHDOG PORT3 TIMER...
Page 46: Outline Of Function
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.8 Outline of Function µ PD78011B µ PD78012B µ PD78013 µ PD78014 µ PD78P014 Part Number Item Internal Mask ROM One-time memory PROM/EPROM 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes Note 1 Note 2 High-speed RAM...
Page 47: Differences Among Μ Pd78011B, 78012B, 78013, 78014 And Μ Pd78011B(A), 78012B(A), 78013(A), 78014(A)
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) µ PD78011B µ PD78012B µ PD78013 µ PD78014 µ PD78P014 Part Number Item Timer output 3 outputs: (14-bit PWM generation possible from one output) Clock output 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (@ 10.0 MHz with main system clock) 32.768 kHz (@ 32.768 kHz with subsystem clock) Buzzer output...
Page 48: Mask Options
CHAPTER 1 OUTLINE ( µ PD78014 Subseries) 1.10 Mask Options The mask ROM versions ( µ PD78011B, µ PD78012B, µ PD78013, µ PD78014) have the mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 1-2 can be incorporated. When these resistors are necessary, the number of external components and mounting space can be saved by utilizing the mask options.
Page 49: Chapter 2 Outline ( Μ Pd78014Y Subseries)
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 2.1 Features • On-chip large-capacity ROM and RAM Item Program Memory Data Memory Part (ROM) Internal high-speed RAM Buffer RAM Number µ PD78011BY 8 Kbytes 512 bytes 32 bytes µ...
Page 50: Application Fields
Remark ××× is the ROM code suffix. Please refer to the Quality grade on NEC Semiconductor Devices (C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 51: Pin Configurations (Top View)
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 2.5 Pin Configurations (Top View) (1) Normal operating mode • 64-pin plastic shrink DIP (750 mils) µ PD78011BYCW-×××, 78012BYCW-××× µ PD78013YCW-×××, 78014YCW-×××, 78P014YCW • 64-pin ceramic shrink DIP with window (750 mils) µ PD78P014YDW P20/SI1 P21/SO1 P22/SCK1...
Page 52 CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 64-pin plastic QFP (14 × 14 mm) • µ PD78011BYGC-×××-AB8, 78012BYGC-×××-AB8 µ PD78013YGC-×××-AB8, 78014YGC-×××-AB8, 78P014YGC-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P30/TO0 P11/ANI1 P31/TO1 P10/ANI0 P32/TO2...
Page 53 CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) A8 to A15 : Address Bus : Read Strobe AD0 to AD7 : Address/Data Bus RESET : Reset ANI0 to ANI7 : Analog Input SB0, SB1 : Serial Bus ASTB : Address Strobe SCK0, SCK1 : Serial Clock : Analog Power Supply...
Page 54 CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) (2) PROM programming mode • 64-pin plastic shrink DIP (750 mils) µ PD78P014YCW • 64-pin ceramic shrink DIP with window (750 mils) µ PD78P014YDW Open Open www.DataSheet4U.com RESET Cautions 1. (L) : Connect individually to V via a pull-down resistor.
Page 55 CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 64-pin plastic QFP (14 × 14 mm) • µ PD78P014YGC-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Open Open RESET www.DataSheet4U.com 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Cautions 1.
Page 56: Series Expansion
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 2.6 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Mass-produced products Products under development The subseries whose names end with Y support the I C bus specifications Control µ...
Page 57 CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) The following table shows the differences among Y subseries functions. Function Configuration of Serial Interface MIN. Part number Capacity Value µ PD78075BY Control 32K to 40K 3-wire/2-wire/I : 1ch 1.8 V µ PD78078Y 48K to 60K 3-wire with automatic transmit/receive function : 1ch µ...
Page 58: Block Diagram
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 2.7 Block Diagram TO0/P30 16-bit TIMER/ EVENT COUNTER TI0/INTP0/P00 PORT0 P01 to P03 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 PORT1 P10 to P17 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 PORT2 P20 to P27 WATCHDOG PORT3 TIMER...
Page 59: Outline Of Function
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 2.8 Outline of Function µ PD78011BY µ PD78012BY µ PD78013Y µ PD78014Y µ PD78P014Y Part Number Item Internal Mask ROM One-time memory PROM/EPROM Note 1 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes High-speed RAM 512 bytes...
Page 60 CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) µ PD78011BY µ PD78012BY µ PD78013Y µ PD78014Y µ PD78P014Y Part Number Item Timer output 3 outputs: (14-bit PWM generation possible from one output) Clock output 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (@ 10.0 MHz with main system clock) 32.768 kHz (@ 32.768 kHz with subsystem clock) Buzzer output...
Page 61: Mask Options
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries) 2.9 Mask Options The mask ROM versions ( µ PD78011BY, µ PD78012BY, µ PD78013Y, µ PD78014Y) have mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 2-1 can be incorporated.
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Page 63: Pin Function ( Μ Pd78014 Subseries)
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name Input/ Function After Alternate Output Reset Function Input Port 0 Input only Input INTP0/TI0...
Page 64 CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) (1) Port pins (2/2) Pin Name Input/ Function After Alternate Output Reset Function P40 to P47 Input/ Port 4 Input AD0 to AD7 Output 8-bit input/output port. Input/output specifiable in 8-bit wise. When used as an input port, an on-chip pull-up resistor can be connected by software.
Page 65 CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) (2) Non-Port Pins (1/2) Pin Name Input/ Function After Alternate Output Reset Function INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI0 INTP1 edge, falling edge, both rising and falling edges). INTP2 INTP3 External interrupt request input with falling edge detection...
Page 66: Prom Programming Mode Pins ( Μ Pd78P014 Only)
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) (2) Non-Port Pins (2/2) Pin Name Input/ Function After Alternate Output Reset Function ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 Input A/D converter reference voltage input. — —...
Page 67: Description Of Pin Functions
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P04 (Port 0) These are 5-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input and crystal connection for subsystem clock oscillation.
Page 68: P10 To P17 (Port 1)
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 69: P20 To P27 (Port 2)
(a) SI0, SI1, SO0, SO1 Serial interface serial data input/output pins (b) SCK0 and SCK1 Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins (d) BUSY www.DataSheet4U.com Serial interface automatic transmit/receive busy input pins (e) STB...
Page 70: P30 To P37 (Port 3)
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 71: P40 To P47 (Port 4)
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. Test input flag (KRIF) is set to 1 by falling edge detection. The following operating modes can be specified in 8-bit units.
Page 72: P60 To P67 (Port 6)
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.2.7 P60 to P67 (Port 6) These are 8-bit output dedicated ports. Besides serving as input/output port, they have control functions in external memory expansion mode. P60 to P63 can drive LEDs directly. The following operating modes can be specified bit-wise.
Page 73: Xt1 And Xt2
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.2.13 XT1 and XT2 Crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 3.2.14 V Positive power supply pin 3.2.15 V Ground potential pin ( µ...
Page 74: Input/Output Circuit And Recommended Connection Of Unused Pins
CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) 3.3 Input/Output Circuit and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
Page 75 CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Input/Output Recommended Connection for Unused Pins Circuit Type RESET Input — — Leave open — Connect to V Connect to V Connect to V IC (Mask ROM Version) Connect directly to V (PROM Version)
Page 76 CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) Figure 3-1. Pin Input/Output Circuit List (1/2) Type 2 Type 8-A pull-up P-ch enable data P-ch IN/OUT output N-ch Schmitt-triggered input with hysteresis characteristics disable Type 5-A Type 10-A pull-up pull-up P-ch P-ch enable enable...
Page 77 CHAPTER 3 PIN FUNCTION ( µ PD78014 Subseries) Figure 3-1. Pin Input/Output Circuit List (2/2) Type 13 Type 16 feedback IN / OUT cut-off data P-ch N-ch output disable Middle-High Voltage Input Buffer Type 13-B Mask Option IN / OUT data N-ch output disable...
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Page 79: Pin Function ( Μ Pd78014Y Subseries)
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name Input/ Function After Alternate Output Reset Function Input Port 0 Input only Input INTP0/TI0...
Page 80 CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) (1) Port pins (2/2) Pin Name Input/ Function After Alternate Output Reset Function P40 to P47 Input/ Port 4 Input AD0 to AD7 Output 8-bit input/output port. Input/output specifiable in 8-bit units. When used as an input port, an on-chip pull-up resistor can be connected by software.
Page 81 CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) (2) Non-Port Pins (1/2) Pin Name Input/ Function After Alternate Output Reset Function INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI0 INTP1 edge, falling edge, both rising and falling edges). INTP2 INTP3 External interrupt request input with falling edge detection.
Page 82: Prom Programming Mode Pins ( Μ Pd78P014Y Only)
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) (2) Non-Port Pins (2/2) Pin Name Input/ Function After Alternate Output Reset Function ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 Input A/D converter reference voltage input. — —...
Page 83: Description Of Pin Functions
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P04 (Port 0) These are 5-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input and crystal connection for subsystem clock oscillation.
Page 84: P10 To P17 (Port 1)
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 85: P20 To P27 (Port 2)
(a) SI0, SI1, SO0, SO1, SDA0, SDA1 Serial interface serial data input/output pins (b) SCK0, SCK1, SCL Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins (d) BUSY www.DataSheet4U.com Serial interface automatic transmit/receive busy input pins (e) STB...
Page 86: P30 To P37 (Port 3)
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 87: P40 To P47 (Port 4)
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. The test input flag (KRIF) is set to 1 by falling edge detection. The following operating modes can be specified in 8-bit units.
Page 88: P60 To P67 (Port 6)
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.2.7 P60 to P67 (Port 6) These are 8-bit input/output ports. Besides serving as an input/output port, they have control functions in external memory expansion mode. P60 to P63 can drive LEDs directly. The following operating modes can be specified bit-wise.
Page 89: Xt1 And Xt2
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.2.13 XT1 and XT2 Crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 4.2.14 V Positive power supply pin 4.2.15 V Ground potential pin ( µ...
Page 90: Input/Output Circuit And Recommended Connection Of Unused Pins
CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) 4.3 Input/Output Circuit and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1.
Page 91 CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Input/Output Recommended Connection for Unused Pins Circuit Type RESET Input — — Leave open — Connect to V Connect to V Connect to V IC (Mask ROM Version) Connect directly to V (PROM Version)
Page 92 CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) Figure 4-1. Pin Input/Output Circuit List (1/2) Type 2 Type 8-A pull-up P-ch enable data P-ch IN/OUT output N-ch Schmitt-triggered input with hysteresis characteristics disable Type 5-A Type 10-A pull-up pull-up P-ch P-ch enable enable...
Page 93 CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) Figure 4-1. Pin Input/Output Circuit List (2/2) Type 13 Type 16 feedback IN / OUT cut-off data P-ch N-ch output disable Middle-High Voltage Input Buffer Type 13-B Mask Option IN / OUT data N-ch output disable...
Page 94 CHAPTER 4 PIN FUNCTION ( µ PD78014Y Subseries) [MEMO] www.DataSheet4U.com...
Page 95: Chapter 5 Cpu Architecture
CHAPTER 5 CPU ARCHITECTURE CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces The µ PD78014 and 78014Y Subseries can each access a memory space of 64 Kbytes. Figures 5-1 to 5-5 show memory maps. Figure 5-1. Memory Map ( µ PD78011B, 78011BY) FFFFH Special Function Registers (SFR)
Page 96 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map ( µ PD78012B, 78012BY) FFFFH Special Function Registers (SFR) 256 × 8 bits F F 0 0 H General Registers FEFFH 32 × 8 bits FEE0H FEDFH Internal High-Speed RAM 512 × 8 bits 3FFFH FD00H FCFFH...
Page 97 CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( µ PD78013, 78013Y) FFFFH Special Function Registers (SFR) 256 × 8 bits F F 0 0 H General Registers FEFFH 32 × 8 bits FEE0H FEDFH Internal High-Speed RAM 1024 × 8 bits 5FFFH FB00H FAFFH...
Page 98 CHAPTER 5 CPU ARCHITECTURE Figure 5-4. Memory Map ( µ PD78014, 78014Y) FFFFH Special Function Registers (SFR) 256 × 8 bits F F 0 0 H General Registers FEFFH 32 × 8 bits FEE0H FEDFH Internal High-Speed RAM 1024 × 8 bits 7FFFH FB00H FAFFH...
Page 99 CHAPTER 5 CPU ARCHITECTURE Figure 5-5. Memory Map ( µ PD78P014, 78P014Y) FFFFH Special Function Registers (SFR) 256 × 8 bits F F 0 0 H General Registers FEFFH 32 × 8 bits FEE0H FEDFH Internal High-Speed RAM 1024 × 8 bits 7FFFH FB00H FAFFH...
Page 100: Internal Program Memory Space
CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space Internal program memory store programs and table data. Normally, they are addressed with a program counter (PC). The µ PD78014 and 78014Y Subseries contain internal ROM (or PROM) in each product having the capacities shown below.
Page 101: Internal Data Memory Space
CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µ PD78014 and 78014Y Subseries incorporate the following RAMs. (1) Internal high-speed RAM The µ PD78014 and 78014Y Subseries incorporate the following capacity of internal high-speed RAM in each product. Table 5-3.
Page 102: Processor Registers
CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µ PD78014 and 78014Y Subseries incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. A program counter (PC), a program status word (PSW) and a stack pointer (SP) are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 103 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag.
Page 104 CHAPTER 5 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Internal high-speed RAM of each product is as follows. µ...
Page 105 CHAPTER 5 CPU ARCHITECTURE Figure 5-9. Data to be Saved to Stack Memory PUSH rp Instruction CALL, CALLF, and Interrupt and CALLT Instruction BRK Instruction SP←SP–3 ↑ SP–3 PC7 to PC0 SP←SP–2 SP←SP–2 ↑ ↑ ↑ Register Pair Lower PC7 to PC0 SP–2 PC15 to PC8 SP–2...
Page 106: General Registers
CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register.
Page 107 CHAPTER 5 CPU ARCHITECTURE Figure 5-11. General Register Configuration (a) Absolute Name 16-Bit Processing 8-Bit Processing F E F F H BANK0 F E F 8 H F E F 7 H BANK1 F E F 0 H F E E F H BANK2 F E E 8 H F E E 7 H...
Page 108: Special Function Register (Sfr)
CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function register can be manipulated, like the general register, with the operation, transfer and bit manipulation instructions.
Page 109 CHAPTER 5 CPU ARCHITECTURE Table 5-5. Special Function Register List (1/2) Address Special Function Register (SFR) Name Symbol Manipulatable When Bit Unit Reset 1 Bit 8 Bits 16 Bits FF00H Port 0 — FF01H Port 1 — FF02H Port 2 —...
Page 110 CHAPTER 5 CPU ARCHITECTURE Table 5-5. Special Function Register List (2/2) Address Special Function Register (SFR) Name Symbol Manipulatable When Bit Unit Reset 1 Bit 8 Bits 16 Bits FF60H Serial operating mode register 0 CSIM0 — FF61H Serial bus interface control register SBIC —...
Page 111: Instruction Address Addressing
CHAPTER 5 CPU ARCHITECTURE 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 112: Immediate Addressing
CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL ! addr16, BR ! addr16, or CALLF ! addr11 instruction is executed. CALL ! addr16 and BR ! addr16 instructions can branch to all the memory spaces.
Page 113 CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
Page 114: Register Addressing
CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] www.DataSheet4U.com...
Page 115: Operand Address Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing 5.4.1 Data memory addressing Addressing is a method to specify the instruction address to be executed next and the register and memory address to be manipulated when instructions are executed. The instruction address to be executed next is addressed by the program counter (PC) (for details, refer to 5.3 Instruction Address Addressing).
Page 116 CHAPTER 5 CPU ARCHITECTURE Figure 5-13. Data Memory Addressing ( µ PD78012B, 78012BY) F F F F H Special Function SFR addressing Registers (SFR) 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General Registers Register addressing...
Page 117 CHAPTER 5 CPU ARCHITECTURE Figure 5-14. Data Memory Addressing ( µ PD78013, 78013Y) F F F F H Special Function SFR addressing Registers (SFR) 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General Registers Register addressing...
Page 118 CHAPTER 5 CPU ARCHITECTURE Figure 5-15. Data Memory Addressing ( µ PD78014, 78014Y) F F F F H Special Function SFR addressing Registers (SFR) 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General Registers Register addressing...
Page 119 CHAPTER 5 CPU ARCHITECTURE Figure 5-16. Data Memory Addressing ( µ PD78P014, 78P014Y) F F F F H Special Function SFR addressing Registers (SFR) 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General Registers Register addressing...
Page 120: Implied Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.2 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed. Of the µ PD78014 and 78014Y Subseries instruction words, the following instructions employ implied addressing. Instruction Register to be Specified by Implied Addressing MULU...
Page 121: Register Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.3 Register addressing [Function] The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn and RPn) in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 122: Direct Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.4 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] dentifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, ! 0FE00H; when setting ! addr16 to FE00H Instruction code 1 OP code [Illustration]...
Page 123: Short Direct Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.5 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high- speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 124 CHAPTER 5 CPU ARCHITECTURE [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Instruction code 0 OP code 30H (saddr-offset) 50H (immediate data) [Illustration] OP code saddr-offset Short Direct Memory α Effective address When 8-bit immediate data is 20H to FFH, α = 0 When 8-bit immediate data is 00H to 1FH, α...
Page 125: Special Function Register (Sfr) Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.6 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 126: Register Indirect Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.7 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code.
Page 127: Based Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1).
Page 128: Based Indexed Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.9 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1).
Page 129: Chapter 6 Port Functions
CHAPTER 6 PORT FUNCTIONS CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78014 and 78014Y Subseries each incorporate two input ports and fifty-one input/output ports. Figure 6-1 shows the port types. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
Page 130 CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions ( µ PD78014 Subseries) (1/2) Pin Name Function Alternate Function Port 0. Input only. INTP0/TI0 5-bit input/output port. Input/output specifiable bit-wise. INTP1 If used as an input port, on-chip pull-up INTP2 resistor can be enabled by software. INTP3 Input only.
Page 131 CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions ( µ PD78014 Subseries) (2/2) Pin Name Function Alternate Function Port 6. N-ch open-drain input/output port. On-chip — 8-bit input/output port. pull-up resistor can be specified by mask Input/output specifiable bit-wise. option only for mask ROM versions. LED can be driven directly.
Page 132 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD78014Y Subseries) (1/2) Pin Name Function Alternate Function Port 0. Input only. INTP0/TI0 5-bit input/output port. Input/output specifiable bit-wise. INTP1 If used as an input port, on-chip pull-up INTP2 resistor can be enabled by software. INTP3 Input only.
Page 133 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD78014Y Subseries) (2/2) Pin Name Function Alternate Function Port 6. N-ch open-drain input/output port. On-chip — 8-bit input/output port. pull-up resistor can be specified by mask Input/output specifiable bit-wise. option only for mask ROM versions. LED can be driven directly.
Page 134: Port Block Diagram
CHAPTER 6 PORT FUNCTIONS 6.2 Port Block Diagram A port consists of the following hardware. Table 6-3. Port Block Diagram Item Configuration Control register Port mode register (PMm: m = 0, 1, 2, 3, 5, 6) Pull-up resistor option register (PUO) Note Memory expansion mode register...
Page 135 CHAPTER 6 PORT FUNCTIONS Figure 6-3. P01 to P03 Block Diagrams PUO0 P-ch Selector PORT Output Latch P01/INTP1 to P03/INTP3 (P01 to P03) PM01 to PM03 PUO : Pull-up resistor option register : Port mode register : Port 0 read signal www.DataSheet4U.com WR : Port 0 write signal Figure 6-4.
Page 136: Port 1
CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. P10 to P17 pins can be set to the input mode/output mode bit-wise with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO).
Page 137: Port 2 ( Μ Pd78014 Subseries)
CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 ( µ PD78014 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can be set to the input mode/output mode bit-wise with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with an on-chip pull-up resistor option register (PUO).
Page 138 CHAPTER 6 PORT FUNCTIONS Figure 6-7. P22 and P27 Block Diagrams ( µ PD78014 Subseries) PUO2 P-ch Selector PORT Output Latch P22/SCK1, (P22, P27) P27/SCK0 PM22, PM27 Alternate Function PUO : Pull-up resistor option register : Port mode register www.DataSheet4U.com : Port 2 read signal WR : Port 2 write signal...
Page 139: Port 2 ( Μ Pd78014Y Subseries)
CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 ( µ PD78014Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can be set to the input mode/output mode bit-wise with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO).
Page 140 CHAPTER 6 PORT FUNCTIONS Figure 6-9. P22 and P27 Block Diagrams ( µ PD78014Y Subseries) PUO2 P-ch Selector PORT Output Latch P22/SCK1, (P22, P27) P27/SCK0/ PM22, PM27 Alternate Function PUO : Pull-up resistor option register : Port mode register www.DataSheet4U.com : Port 2 read signal WR : Port 2 write signal...
Page 141: Port 3
CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can be set to the input mode/output mode bit-wise with the port mode register (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO).
Page 142: Port 4
CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can be set to the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, a pull- up resistor can be connected to them in 8-bit units with an on-chip pull-up resistor option register (PUO).
Page 143: Port 5
CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can be set to the input mode/output mode bit-wise with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO).
Page 144: Port 6
CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latches. P60 to P67 pins can be set to either input mode or output mode in 1-bit units with port mode register 6 (PM6). This port has the following functions related to the pull-up resistor.
Page 145 CHAPTER 6 PORT FUNCTIONS Figure 6-14. P60 to P63 Block Diagrams Mask Option resistors Mask ROM versions only PD78P014 and 78P014Y have no pull-up resistor. Selector PORT Output Latch P60 to P63 (P60 to P63) PM60 to PM63 : Port mode register : Port 6 read signal WR : Port 6 write signal Figure 6-15.
Page 146: Port Function Control Registers
CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM3, PM5, PM6) • Pull-up resistor option register (PUO) • Memory expansion mode register (MM) •...
Page 147 CHAPTER 6 PORT FUNCTIONS Table 6-5. Port Mode Register and Output Latch Setting when Alternate Function is Used Pin Name Alternate Function PM×× P×× Pin Name Alternate Function PM×× P×× Function Input/ Function Input/ Name Output Name Output × INTP0 Input 1 (defined) None P40 to P47...
Page 148 CHAPTER 6 PORT FUNCTIONS Figure 6-16. Port Mode Register Format Symbol Address When Reset PM03 PM02 PM01 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM37 PM36 PM35 PM34 PM33 PM32 PM31...
Page 149 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUO) This register is used to set whether to use an on-chip pull-up resistor at each port or not. An on-chip pull-up resistor is internally used only for the bits that are set to the input mode at a port where pull-up resistor use has been specified with PUO.
Page 150 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) The registers are used to set port 4 input/output. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 6-18. Memory Expansion Mode Register Format Symbol Address When Reset...
Page 151 CHAPTER 6 PORT FUNCTIONS (4) Key return mode register (KRM) The registers are used to set standby mode release enable/disable with the key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Page 152: Port Function Operations
CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 153: Operations On Input/Output Port
CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
Page 154: Mask Options
CHAPTER 6 PORT FUNCTIONS 6.5 Mask Options Mask ROM versions can contain a pull-up resistor in P60 to P63 pins bit-wise with the mask option. The µ PD78P014 and 78P014Y have no mask option and do not contain a pull-up resistor for P60 to P63 pins. www.DataSheet4U.com...
Page 155: Chapter 7 Clock Generator
CHAPTER 7 CLOCK GENERATOR CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator Oscillates at frequencies of 1.0 to 10.0 MHz.
Page 156 Figure 7-1. Clock Generator Block Diagram XT1/P04 Subsystem clock oscillator Watch timer, clock output function circuit Prescaler Main system Clock to peripheral hardware Prescaler clock oscil- lator circuit Standby Wait CPU clock control control circuit circuit To INTP0 sampling clock STOP PCC2 PCC1 PCC0...
Page 157: Clock Generator Control Register
CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). The PCC sets CPU clock selection, the ratio of division, main system clock oscillator operation/stop and subsystem clock oscillator on-chip feedback resistor enable/disable.
Page 158 CHAPTER 7 CLOCK GENERATOR Figure 7-3. Processor Clock Control Register Format Symbol <7> <6> <5> <4> Address When Reset Note 1 PCC2 PCC1 PCC0 FFFBH PCC2 PCC1 PCC0 CPU Clock (f selection Other than above Setting prohibited CPU Clock Status Main system clock Subsystem clock Subsystem Clock Feedback Resistor Selection...
Page 159 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78014, 78014Y Subseries is executed by the CPU clock 4 clock. The relationship between the CPU clock (f ) and minimum instruction execution time is as shown in Table 7-2. Table 7-2.
Page 160: System Clock Oscillator
CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 10.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and its inverted signal to the X2 pin.
Page 161 CHAPTER 7 CLOCK GENERATOR Cautions 1. When using a main system clock oscillator and a subsystem clock oscillator, wire the portion enclosed in the dotted line areas in Figures 7-4 and 7-5 as follows to avoid adverse influence on the wiring capacitance. •...
Page 162 CHAPTER 7 CLOCK GENERATOR Figure 7-6. Examples of Resonator with Bad Connection (2/2) (c) High fluctuating current close to (d) Current flowing through ground line of signal lines oscillator circuit (potentials at points A, B, and C change.) High current High current (e) Signal extracted www.DataSheet4U.com...
Page 163: Divider
CHAPTER 7 CLOCK GENERATOR 7.4.3 Divider The divider divides the main system clock oscillator output (f ) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows.
Page 164: Clock Generator Operations
CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f • Subsystem clock f • CPU clock f •...
Page 165: Main System Clock Operations
CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 166 CHAPTER 7 CLOCK GENERATOR Figure 7-7. Main System Clock Stop Function (2/2) (b) Operation when MCC is set with main system clock operation “L” “L” Oscillation does not stop. Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock (c) Operation when CSS is set after setting MCC with main system clock operation www.DataSheet4U.com Main System Clock Oscillation...
Page 167: Subsystem Clock Operations
CHAPTER 7 CLOCK GENERATOR 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 µ s when operated at 32.768 kHz) irrespective of bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 168: Changing System Clock And Cpu Clock Settings
CHAPTER 7 CLOCK GENERATOR 7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 169: System Clock And Cpu Clock Switching Procedure
CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-8. System Clock and CPU Clock Switching RESET Interrupt Request Signal System Clock CPU Clock Minimum Maximum Speed Subsystem Clock High-Speed...
Page 170 CHAPTER 7 CLOCK GENERATOR [MEMO] www.DataSheet4U.com...
Page 171: Chapter 8 16-Bit Timer/Event Counter
CHAPTER 8 16-BIT TIMER/EVENT COUNTER CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of On-chip Timer in µ PD78014, 78014Y Subseries This section describes the 16-bit timer/event counter. First an outline of the built-in timer in the µ PD78014 and 78014Y Subseries and the related items are shown in the following. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse width measurement (infrared ray remote control receive function), external event counter or square wave output of any frequency.
Page 172: 16-Bit Timer/Event Counter Functions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operation 16-Bit Timer/ 8-Bit Timer/ Watch Timer Watchdog Event Counter Event Counter Timer Note 1 Note 2 Operation Interval timer 1 channel 2 channels 1 channel 1 channel mode External event counter —...
Page 173: 16-Bit Timer/Event Counter Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) PWM output TM0 can generate 14-bit resolution PWM output. (3) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (4) External event counter TM0 can measure the number of pulses of an externally input signal. (5) Square-wave output TM0 can output a square wave with any selected frequency.
Page 174 Figure 8-1. 16-Bit Timer/Event Counter (Timer Mode) Block Diagram Internal bus 16-bit compare register (CR00) Match Match INTTM0 Note 2 16-bit timer/event counter output TO0/P30 control circuit 16-bit timer register 16-bit timer register lower 8 bits (TM0L) upper 8 bits (TM0H) TI0/P00/ Note 1 Clear...
Page 175 Figure 8-2. 16-Bit Timer/Event Counter (PWM Mode) Block Diagram Internal bus 16-bit compare register (CR00) PWM pulse generator TO0/ 16-bit timer register (TM0) 16-bit capture register (CR01) P30 output TCL06 TCL05 TCL04 TOC01 TOE0 PM30 latch Timer clock select 16-bit timer output Port mode register 3 register 0 control register...
Page 176 Figure 8-3. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram Level F/F (LV0) LVR0 LVS0 TO0/ TOC01 PM30 output latch INTTM0 Edge TI0/P00/ detector INTP0 circuit Active level control ES10, ES11 PWM pulse generator TMC01 to TMC03 TOC01 TMC01 to TMC03 TOE0 Remark The circuitry enclosed by the dotted line is the output control circuit.
Page 177 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) 16-bit compare register (CR00) CR00 is a 16-bit register for which the value set in the CR00 is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM0) is generated if they match. It can be used as the register which holds the interval time when TM0 is set to interval timer operation, and as the register which sets the pulse width when TM0 is set PWM output operation.
Page 178: 16-Bit Timer/Event Counter Control Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4 16-Bit Timer/Event Counter Control Registers The following six types of registers are used to control the 16-bit timer/event counter. • Timer clock select register 0 (TCL0) • 16-bit timer mode control register (TMC0) • 16-bit timer output control register (TOC0) •...
Page 179 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. Timer Clock Select Register 0 Format Symbol <7> Address When Reset TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H TCL03 TCL02 TCL01 TCL00 PCL Output Clock Selection (32.768 kHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz)
Page 180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC0 value to 00H.
Page 181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-5. 16-Bit Timer Mode Control Register Format Symbol <0> Address When Reset TMC0 TMC03 TMC02 TMC01 OVF0 FF48H OVF0 16-Bit Timer Register Overflow Detection Overflow not detected Overflow detected TMC03 TMC02 TMC01 Operating Mode & Clear TO0 Output Timing Interrupt Request Mode Selection...
Page 182 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip- flop (LV0) setting/resetting, the active level in PWM mode, output inversion enabling/disabling in modes other than PWM mode and data output mode.
Page 183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH.
Page 184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) External interrupt mode register (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Remarks 1. INTP0 pin is a dual function pin also used for TI0/P00. 2.
Page 185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) Sampling clock select register (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction.
Page 186: 16-Bit Timer/Event Counter Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations By setting bits 2 and 3 (TMC02 and TMC03) of the 16-bit timer mode control register (TMC0) to 1 and 1, they are operated as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit compare register (CR00) beforehand is used as the interval.
Page 187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Operation Timings Count clock TM0 Count value 0000 0001 0000 0001 0000 0001 Count start Clear Clear CR00 INTTM0 Interrupt request Interrupt request acknowledge acknowledge Interval time Interval time Interval time www.DataSheet4U.com Interval time = (N + 1) ×...
Page 188: Pwm Output Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.2 PWM output operations By setting bits 1 to 3 (TMC01 to 03) of the 16-bit timer mode control register (TMC0) to 1, 0, and 0, they are operated as PWM output. Pulses with the duty rate determined by the value set in 16-bit compare register (CR00) beforehand are output from the TO0/P30 pin.
Page 189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V ) used for D/A conversion with the configuration shown in Figure 8-12 is as follows. 16-bit compare register (CR00) value ×...
Page 190: Pulse Width Measurement Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 Pulse width measurement operations The pulse width of the signal to be input to theINTP0/P00/TI0 pin can be neasured with the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the valid edge of the signal input to the INTP0/P00/TI0 pin.
Page 191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-15. Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 FFFF 0000 TI0 Pin Input CR01 Captured Value INTP0 OVF0 (D1 – D0) × t (10000H –...
Page 192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Pulse width measurement by means of restart When input of a valid edge to the INTP0/P00/TI0 pin is detected, the count value of the 16-bit timer register (TM0) is taken into the 16-bit capture register (CR01), and then the pulse width of the signal input to the INTP0/P00/ TI0 pin is measured by clearing TM0 and restarting the count.
Page 193: External Event Counter Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the INTP0/P00/TI0 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register (INTM0) is input. When the TM0 counted value matches the 16-bit compare register (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM0) is generated.
Page 194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. External Event Counter Operation Timings (with Rising Edge Specified) TI0 Pin Input 0000 0001 0002 0003 0004 0005 N – 1 0000 0001 0002 0003 TM0 Count Value CR00 INTTM0 www.DataSheet4U.com...
Page 195: Square-Wave Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 Square-wave output operation The 16-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the count value preset to the 16-bit compare register (CR00). The TO0/P30 pin output status is inverted at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register to 1.
Page 196: 16-Bit Timer/Event Counter Operating Precautions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 8-20.
Page 197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge. Figure 8-22.
Page 198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) OVF0 flag operation OVF0 flag is set to 1: When clear & start mode on match between TM0 and CR00 is selected ↓ CR00 is set to FFFFH ↓ TM0 is counted up from FFFFH to 0000H Figure 8-23.
Page 199: Chapter 9 8-Bit Timer/Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1 8-Bit Timer/Event Counter Functions For the 8-bit timer/event counter incorporated in the µ PD78014 and 78014Y Subseries, the following two modes are available. • 8-bit timer/event counter mode : two-channel 8-bit timer/event counters to be used separately •...
Page 200 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution (102.4 µ s) × 1/f × 1/f × 1/f (400 ns) (400 ns) ×...
Page 201 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution...
Page 202: 16-Bit Timer/Event Counter Mode
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum Interval Time Resolution ×...
Page 203 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter Minimum Pulse Width Maximum Pulse Width...
Page 204: 8-Bit Timer/Event Counter Configuration
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counter consists of the following hardware. Table 9-5. 8-Bit Timer/Event Counter Configuration Item Configuration 8-bits × 2 (TM1, TM2) Timer register Register 8-bit compare register: 2 (CR10, CR20) Timer output 2 (TO1, TO2) Control registers...
Page 205 Figure 9-1. 8-Bit Timer/Event Counter Block Diagram Internal Bus INTTM1 8-Bit Compare 8-Bit Compare Register (CR10) Register (CR20) Note Match 8-Bit Timer/Event TO2/P32 Counter Output Match Control Circuit 2 /2 to 8-Bit Timer Register 1 (TM1) 8-Bit Timer TI1/P33 Clear Register 1 (TM2) INTTM2 Clear...
Page 206 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-2. 8-Bit Timer/Event Counter Output Control Circuit 1 Block Diagram Level F/F (LV1) LVR1 TO1/P31 LVS1 TOC11 Note PM31 Output Latch INTTM1 TOE1 Note Bit 1 of the port mode register 3 (PM3) Remark The section in the broken line is an output control circuit.
Page 207: 8-Bit Timer/Event Counter Control Registers
CHAPTER 9 8-BIT TIMER/EVENT COUNTER (1) 8-bit compare registers (CR10, CR20) These are 8-bit registers that compare the value set to CR10 with the 8-bit timer register 1 (TM1) count value, and the value set to CR20 with the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively).
Page 208 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-4. Timer Clock Select Register 1 Format Symbol Address When Reset TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 FF41H TCL13 TCL12 TCL11 TCL10 8-bit Timer Register 1 Clock Selection TI1 falling edge TI1 rising edge (2.5 MHz) (1.25 MHz)
Page 209 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer registers 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H.
Page 210 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2.
Page 211 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P31/TO1 and P32/TO2 pins for timer output, set output latches PM31, PM32, and P31, P32 to PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 212: 8-Bit Timer/Event Counter Operations
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4 8-Bit Timer/Event Counter Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers (CR10 and CR20). When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Page 213 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Table 9-6. 8-Bit Timer/Event Counter 1 Interval Times TCL13 TCL12 TCL11 TCL10 Minimum Interval Time Maximum Interval Time Resolution × TI1 input cycle TI1 input cycle TI1 input edge cycle × TI1 input cycle TI1 input cycle TI1 input edge cycle ×...
Page 214 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input.
Page 215 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation The 8-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the value preset to 8-bit compare registers (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is inverted at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1.
Page 216: 16-Bit Timer/Event Counter Mode
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is selected. The count clocks are selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register (TCL1). The overflow signal of 8-bit timer/event counter 1 (TM1) becomes a count clock of 8-bit timer/event counter 2 (TM2).
Page 217 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
Page 218 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input. When TM1 overflows, TM2 is incremented with the overflow signal as the count clock.
Page 219 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation The 8-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the value preset to 8-bit compare registers (CR10 and CR20). When setting the count value, the upper 8- bit value is set as CR20 and the lower 8-bit value as CR10.
Page 220: Cautions On 8-Bit Timer/Event Counter Operating
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.5 Cautions on 8-Bit Timer/Event Counter Operating (1) Timer start errors An error of one clock maximum may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the count pulse.
Page 221 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value after CR10 and CR20 (M) change is smaller than that before change (N), it is necessary to restart the timer after changing CR10 and CR20.
Page 222 CHAPTER 9 8-BIT TIMER/EVENT COUNTER [MEMO] www.DataSheet4U.com...
Page 223: Chapter 10 Watch Timer
CHAPTER 10 WATCH TIMER CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 8.38 MHz main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.
Page 224: Watch Timer Configuration
CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Configuration 5 bits × 1 Counter Control register Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer.
Page 225 Figure 10-1. Watch Timer Block Diagram TMC21 Clear 5-Bit Counter Prescaler INTWT Clear INTTM3 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 TCL24 Timer Clock Select Register 2 Watch Timer Mode Control Register Internal Bus...
Page 226 CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format Symbol Address When Reset TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz)
Page 227 CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H.
Page 228: Watch Timer Operations
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768 kHz subsystem clock or 8.38 kHz main system clock is used, the timer operates as a watch timer with a 0.5 second or 0.25 second interval. In addition, when the 4.19 MHz main system clock is used, the timer can operate as a watch timer with a 0.5 second or 1 second interval.
Page 229: Interval Timer Operation
CHAPTER 10 WATCH TIMER 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register (TMC2).
Page 230 CHAPTER 10 WATCH TIMER [MEMO] www.DataSheet4U.com...
Page 231: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (the watchdog timer and the interval timer cannot be used simultaneously).
Page 232: Watchdog Timer Configuration
CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) www.DataSheet4U.com...
Page 233 Figure 11-1. Watchdog Timer Block Diagram Internal Bus TMMK4 8-Bit Prescaler INTWDT TMIF4 Maskable Interrupt Clear Request Control 8-Bit Counter RESET Circuit INTWDT Non-Maskable Interrupt Request TCL22 TCL21 TCL20 WDTM4 WDTM3 Timer Clock Select Register 2 Watchdog Timer Mode Register Internal Bus...
Page 234: Watchdog Timer Control Registers
CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
Page 235 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Symbol Address When Reset TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz)
Page 236 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register Format Symbol <7>...
Page 237: Watchdog Timer Operations
CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).
Page 238: Interval Timer Operation
CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at intervals of a preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The count clock (or interval time) can be selected with bits 0 to 2 (TCL20 to TCL22) of the time clock select register (TCL2).
Page 239: Chapter 12 Clock Output Control Circuit
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin.
Page 240: Clock Output Control Circuit Configuration
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Configuration Control register Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 12-2.
Page 241 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format Symbol <7> Address When Reset CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H TCL03 TCL02 TCL01 TCL00 PCL Output Clock Selection (32.768 kHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz)
Page 242 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in bit-wise. When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 243: Chapter 13 Buzzer Output Control Circuit
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs a square wave with a frequency of either 2.4 kHz, 4.9 kHz, or 9.8 kHz. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.
Page 244: Buzzer Output Function Control Registers
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.
Page 245 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Symbol Address When Reset TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz)
Page 246 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 247: Chapter 14 A/D Converter
CHAPTER 14 A/D CONVERTER CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
Page 248 Figure 14-1. A/D Converter Block Diagram Internal Bus A/D Converter Input Selection Register ADIS3 ADIS2 ADIS1 ADIS0 Series Resistor String ANI0/P10 ANI1/P11 Sample and Hold Circuit ANI2/P12 Voltage Comparator ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 Successive Approxi- ANI7/P17 mation Register ADM1 to ADM3 Falling Edge Detection INTP3/P03...
Page 249 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR).
Page 250 CHAPTER 14 A/D CONVERTER (7) AV This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV . If the voltage to be input to the AV pin is adjusted to the AV level in the standby mode, the current in the series resistor string will be decreased.
Page 251: A/D Converter Control Registers
CHAPTER 14 A/D CONVERTER 14.3 A/D Converter Control Registers The following two types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger.
Page 252 CHAPTER 14 A/D CONVERTER Figure 14-2. A/D Converter Mode Register Format Symbol <7> <6> Address When Reset ADM3 ADM2 ADM1 FF80H ADM3 ADM2 ADM1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Note 1 A/D Conversion Time Selection When operated at When operated at When operated at...
Page 253 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. The pins which are not selected for analog input pins can be used as the input/output port. ADIS is set with an 8-bit memory manipulation instruction.
Page 254: A/D Converter Operations
CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).
Page 255 CHAPTER 14 A/D CONVERTER Figure 14-4. A/D Converter Basic Operation Conversion Time Sampling Time A/D Converter Sampling A/D Conversion Operation Conversion Undefined Result Conversion ADCR Result INTAD A/D conversion operations are performed continuously until bit 7 (CS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 256: Input Voltage And Conversion Results
CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in the A/D conversion result register (ADCR)) is expressed by the following expression.
Page 257: A/D Converter Operating Mode
CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode The operating mode is a select mode. One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and start the A/D conversion. The following two ways are available to start A/D conversion.
Page 258 CHAPTER 14 A/D CONVERTER (2) A/D conversion by software start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 0 and 1, respectively, A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
Page 259: Cautions On A/D Converter
CHAPTER 14 A/D CONVERTER 14.5 Cautions on A/D Converter (1) Current consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV pin at this time, this current must be cut in order to minimize the overall system power dissipation.
Page 260 CHAPTER 14 A/D CONVERTER (2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above AV or below AV is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate.
Page 261 CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/ D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended.
Page 262 CHAPTER 14 A/D CONVERTER [MEMO] www.DataSheet4U.com...
Page 263: Chapter 15 Serial Interface Channel 0 ( Μ Pd78014 Subseries)
75X/XL, processing time is fast. 78K and 17K Series. • NEC single-chip microcontrollers provide as before. SBI mode SCK0, SB0 or • Enables to configure serial bus with two signal lines,...
Page 264: Serial Interface Channel 0 Functions
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1) (See Figure 15-1). The SBI mode complies with the NEC serial bus format and distinguishes the transfer data into “address”, “command”, and “data” to transmit or receive the data.
Page 265 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-1. Serial Bus Interface (SBI) System Configuration Example Master CPU Slave CPU1 SCK0 SCK0 Slave CPU2 SCK0 Slave CPUn SCK0 www.DataSheet4U.com (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level.
Page 266 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-2. Serial Bus Configuration Example with 2-Wire Serial I/O Master CPU Slave SCK0 SCK0 SB0 (SB1) SB0 (SB1) www.DataSheet4U.com...
Page 267: Serial Interface Channel 0 Configuration
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) 15.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 15-3. Serial Interface Channel 0 Configuration Item Configuration Register Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control register Timer clock select register 3 (TCL3)
Page 268 Figure 15-3. Serial Interface Channel 0 Block Diagram Internal Bus Serial Bus Interface Serial Operating Mode Register 0 Control Register CSIE0 COI WUP CSIM CSIM CSIM CSIM CSIM Slave Address BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Register (SVA) SVAM Match Control Circuit...
Page 269 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
Page 270 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
Page 271: Serial Interface Channel 0 Control Registers
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) 15.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 272 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-4. Timer Clock Select Register 3 Format Symbol Address When Reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection 2 Note (1.25 MHz)
Page 273 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-5. Serial Operating Mode Register 0 Format (1/2) Symbol <7> <6> <5> Address When Reset Note 1 CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection ×...
Page 274 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-5. Serial Operating Mode Register 0 Format (2/2) Note Slave Address Comparison Result Flag Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data CSIE0 Serial Interface Channel 0 Operation Control Operation stopped...
Page 275 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-6. Serial Bus Interface Control Register Format (2/2) CMDD Command Detection Clear Conditions (CMDD = 0) Set Conditions (CMDD = 1) • When transfer start instruction is executed • When command signal (CMD) is detected •...
Page 276 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (4) Interrupt timing specification register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Page 277: Serial Interface Channel 0 Operations
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) 15.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode •...
Page 278: 3-Wire Serial I/O Mode Operation
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) 15.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 279 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27...
Page 280 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 281 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization of the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
Page 282 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (3) Various signals Figure 15-9 shows RELT and CMDT operations. Figure 15-9. RELT and CMDT Operations SO0 Latch RELT CMDT (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 15-10 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus.
Page 283: Sbi Mode Operation
15.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI has a format with the bus configuration function added to the clocked serial I/O method so that it can carry out communication with two or more devices with two signal conductors on the single-master high-speed serial bus.
Page 284 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-11. Example of Serial Bus Configuration with SBI Serial Clock SCK0 SCK0 Slave CPU Master CPU Serial Data Bus SB0 (SB1) SB0 (SB1) Address 1 SCK0 Slave CPU SB0 (SB1) Address 2 SCK0 Slave IC...
Page 285 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (1) SBI functions In the conventional serial I/O method, when a serial bus is constructed by connecting two or more devices, many ports and wiring are necessary to distinguish chip select signals and command/data and to judge the busy state because only the data transfer function is available.
Page 286 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-12. SBI Transfer Timings Address Transfer SCK0 BUSY SB0 (SB1) Bus Release Address Signal Command Transfer Command Signal SCK0 SB0 (SB1) BUSY READY Command Data Transfer SCK0 SB0 (SB1) BUSY READY www.DataSheet4U.com...
Page 287 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (a) Bus release signal (REL) The bus release signal is generated when the SCK0 line is in high level (a serial clock is not output) and the SB0 (SB1) line changes from low level to high level. The bus release signal is output by the master.
Page 288 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (c) Address The address is 8-bit data that the master outputs to the slave connected to the bus line to select a specific slave. Figure 15-15. Address SCK0 SB0 (SB1) Address Bus Release Signal Command Signal...
Page 289 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (d) Command and Data The master sends commands and sends/receives data to the slave selected by sending the address. Figure 15-17. Command SCK0 SB0 (SB1) Command Command Signal Figure 15-18. Data SCK0 SB0 (SB1) Data...
Page 290 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (e) Acknowledge signal (ACK) This signal is used between the sending side and receiving side devices for confirmation of correct serial data sending. Figure 15-19. Acknowledge Signal (When output synchronously with SCK0 in 11th clock.) SCK0 SB0 (SB1) (When output synchronously with SCK0 in 9th clock.)
Page 291 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (f) Busy signal (BUSY), Ready signal (READY) The busy signal informs the master that the slave is busy transmitting/receiving data. The ready signal informs the master that the slave is ready to transmit/receive data. Figure 15-20.
Page 292 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27...
Page 293 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 294 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (continued) ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion Acknowledge signal is output in synchronization with the 9th clock of transfer falling edge of SCK0 (automatically output when ACKE = 1).
Page 295 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> Address When Reset Note 1 SINT SVAM...
Page 296 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (4) Various signals Figures 15-21 to 15-26 show various signals in SBI and flag operations of the serial bus interface control register (SBIC). Table 15-4 lists various signals in SBI. Figure 15-21.
Page 297 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-23. ACKT Operation SCK0 SB0 (SB1) ACK signal is output a period of one clock immediately after setting ACKT When set during this period Caution Do not set ACKT before termination of transfer. www.DataSheet4U.com...
Page 298 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-24. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 SB0 (SB1) ACK signal is output at 9th clock ACKE When ACKE = 1 at this point (b) When set after completion of transfer SCK0 SB0 (SB1)
Page 299 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Figure 15-25. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 Transfer Start Instruction SIO0 Transfer Start SCK0 SB0 (SB1) ACKD (b) When ACK signal is output after 9th clock of SCK0 Transfer Start Instruction SIO0 Transfer Start...
Page 300 Table 15-4. Various Signals in SBI Mode (1/2) Signal Name Output Definition Timing Chart Output Condition Effects on Flag Meaning of Signal Device Bus release Master SB0 (SB1) rising edge • RELT set • RELD set CMD signal is output to SCK0 “H”...
Page 301 Table 15-4. Various Signals in SBI Mode (2/2) Signal Name Output Definition Timing Chart Output Condition Effects on Flag Meaning of Signal Device Serial clock Master Synchronous clock to When CSIE0 = 1, CSIIF0 set (rising Timing of signal output (SCK0) output address/command/ execution of...
Page 302 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 .... Serial clock input/output pin <1> Master .. CMOS and push-pull output <2>...
Page 303 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (6) Address match detection method In the SBI mode, a particular slave device can be selected by sending a slave address from the master device. Address match detection is automatically executed by hardware. With the slave address register (SVA), and if the wake-up function specification bit (WUP) = 1, CSIIF0 is set only when the selve address transmitted from the master device matches the value set in SVA.
Page 304 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (8) Communication operation In the SBI mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an “address” to the serial bus. After the communication target device has been determined, commands and data are transmitted/ received and serial communication is realized between the master and slave devices.
Page 305 Figure 15-28. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) Interrupt Servicing CMDT RELT CMDT Write Program Processing (Preparation for the Next Serial Transfer) to SIO0 INTCSI0 ACKD SCK0 Hardware Operation Serial Transmission Generation Stop Transfer Line...
Page 306 Figure 15-29. Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Interrupt Servicing CMDT Write Program Processing to SIO0 (Preparation for the Next Serial Transfer) INTCSI0 ACKD SCK0 Hardware Operation Serial Transmission Generation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY...
Page 307 Figure 15-30. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Write Interrupt Servicing Program Processing to SIO0 (Preparation for the Next Serial Transfer) INTCSI0 ACKD SCK0 Hardware Operation Serial Transmission Generation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY...
Page 308 Figure 15-31. Data Transmission from Slave Device to Master Device Master Device Processing (Receiver) FFH Write SIO0 ACKT FFH Write Receive Data Processing Program Processing to SIO0 Read to SIO0 SCK0 INTCSI0 Serial Hardware Operation Serial Reception Stop Generation Output Reception Transfer Line SCK0 Pin...
Page 309 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...
Page 310: 2-Wire Serial I/O Mode Operation
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (c) In the SBI mode, the BUSY signal is output until the falling of the next serial clock after the BUSY release indication. If WUP = 1 is set by mistake during this period, BUSY will not be released. Thus, after releasing BUSY, be sure to check that the SB0 (SB1) has become high level before setting WUP = 1.
Page 311 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC) and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 312 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27...
Page 313 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 314 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> Address When Reset SINT SVAM FF63H...
Page 315 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 316 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (3) Various signals Figure 15-34 shows RELT and CMDT operations. Figure 15-34. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 317: Sck0/P27 Pin Output Manipulation
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SBI) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred.
Page 318 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries) [MEMO] www.DataSheet4U.com...
Page 319: Chapter 16 Serial Interface Channel 0 ( Μ Pd78014Y Subseries)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) The µ PD78014Y Subseries incorporates two channels of clock synchronous serial interfaces. Differences between channels 0 and 1 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1) .
Page 320 75X/XL, processing time is fast. 78K and 17K series. • NEC single-chip microcontrollers provided as before. SBI mode SCK0, SB0 or • Enables configuration of serial bus with two signal...
Page 321: Serial Interface Channel 0 Functions
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1) (see Figure 16-1). The SBI mode complies with the NEC serial bus format and distinguishes the transfer data into “address”, “command”, and “data” to transmit or receive the data.
Page 322 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-1. Serial Bus Interface (SBI) System Configuration Example Master CPU Slave CPU1 SCK0 SCK0 Slave CPU2 SCK0 Slave CPUn SCK0 www.DataSheet4U.com (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of the serial clock (SCK0) and serial data bus (SB0 or SB1).
Page 323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-2. Serial Bus Configuration Example with 2-Wire Serial I/O Master CPU Slave SCK0 SCK0 SB0 (SB1) SB0 (SB1) www.DataSheet4U.com...
Page 324 This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode complies with the NEC I C bus format. In this mode, the transmitter outputs three kinds of data onto the serial data bus “start condition”, “data”, and “stop condition”.
Page 325: Serial Interface Channel 0 Configuration
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-3. Serial Interface Channel 0 Configuration Item Configuration Register Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control register Timer clock select register 3 (TCL3)
Page 326 Figure 16-4. Serial Interface Channel 0 Block Diagram Internal Bus Serial Bus Interface Serial Operating Mode Register 0 Control Register CSIM CSIE0 COI WUP CSIM CSIM CSIM CSIM Slave Address BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Register (SVA) SVAM Match Control Circuit...
Page 327 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
Page 328 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (3) SO0 latch This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
Page 329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Table 16-4. Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer Mode WAT1 WAT0 ACKE Description 3-wire or 2-wire serial I/O mode An interrupt request signal is generated each time 8 serial clocks are counted.
Page 330: Serial Interface Channel 0 Control Registers
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-5. Timer Clock Select Register 3 Format Symbol Address When Reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Seletion Serial Clock in I C bus mode Serial Clock in 3-wire/SBI/2-wire mode...
Page 332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-6. Serial Operating Mode Register 0 Format (1/2) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection ×...
Page 333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-6. Serial Operating Mode Register 0 Format (2/2) Slave Address Comparison Result Flag Note Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data CSIE0 Serial Interface Channel 0 Operation Control Operation stopped...
Page 334 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-7. Serial Bus Interface Control Register Format (1/2) Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address When Reset Note SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H RELT...
Page 335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-7. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge Signal Automatic Output Control (in SBI mode) Acknowledge signal automatic output disable (output with ACKT enable) Before completion Acknowledge signal is output in synchronization with the 9th clock falling edge of of transfer SCK0 (automatically output when ACKE = 1).
Page 336 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-8. Interrupt Timing Specification Register Format (1/2) Symbol <6> <5> <4> <3> <2> Address When Reset SINT SVAM WREL WAT1 WAT0 FF63H Note 1 WAT1 WAT0 Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
Page 337 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-8. Interrupt Timing Specification Register Format (2/2) SVAM SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 INTCSI0 Interrupt Cause Selection Note 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection in the I C bus mode or termination of serial interface in the...
Page 338: Serial Interface Channel 0 Operations
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode •...
Page 339: 3-Wire Serial I/O Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 340 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) Operating...
Page 341 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 342 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization of the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
Page 343 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (3) Various signals Figure 16-10 shows RELT and CMDT operations. Figure 16-10. RELT and CMDT Operations SO0 Latch RELT CMDT (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 16-11 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus.
Page 344: Sbi Mode Operation
16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI has a format with the bus configuration function added to the clocked serial I/O method so that it can carry out communication with two or more devices with two signal conductors on the single-master high-speed serial bus.
Page 345 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-12. Example of Serial Bus Configuration with SBI Serial Clock SCK0 SCK0 Slave CPU Master CPU Serial Data Bus SB0 (SB1) Address 1 SB0 (SB1) SCK0 Slave CPU SB0 (SB1) Address 2 SCK0 Slave IC...
Page 346 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (1) SBI functions In the conventional serial I/O method, when a serial bus is constructed by connecting two or more devices, many ports and wiring are necessary to distinguish chip select signals and command/data and to judge the busy state because only the data transfer function is available.
Page 347 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-13. SBI Transfer Timings Address Transfer SCK0 BUSY SB0 (SB1) Bus Release Address Signal Command Transfer Command Signal SCK0 SB0 (SB1) BUSY READY Command Data Transfer SCK0 SB0 (SB1) BUSY READY www.DataSheet4U.com...
Page 348 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (a) Bus release signal (REL) The bus release signal is generated when the SCK0 line is in high level (a serial clock is not output) and the SB0 (SB1) line changes from low level to high level. The bus release signal is output by the master.
Page 349 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (c) Address The address is 8-bit data that the master outputs to the slave connected to the bus line to select a specific slave. Figure 16-16. Address SCK0 SB0 (SB1) Address Bus Release Signal Command Signal...
Page 350 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (d) Command and Data The master sends commands and sends/receives data to the slave selected by sending the address. Figure 16-18. Command SCK0 SB0 (SB1) Command Command Signal Figure 16-19. Data SCK0 SB0 (SB1) Data...
Page 351 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (e) Acknowledge signal (ACK) This signal is used between the sending side and receiving side devices for confirmation of correct serial data sending. Figure 16-20. Acknowledge Signal [When output synchronously with SCK0 in 11th clock] SCK0 SB0 (SB1) [When output synchronously with SCK0 in 9th clock]...
Page 352 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (f) Busy signal (BUSY), Ready signal (READY) The busy signal informs the master that the slave is busy transmitting/receiving data. The ready signal informs the master that the slave is ready to transmit/receive data. Figure 16-21.
Page 353 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock selection register 3 (TCL3) Operating...
Page 354 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 355 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (continued) ACKE Acknowledge Signal Automatic Output Control (in the SBI mode) Acknowledge signal automatic output disable (output with ACKT enable) Before completion Acknowledge signal is output in synchronization with the 9th clock of transfer falling edge of SCK0 (automatically output when ACKE = 1).
Page 356 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> <3> <2> Address When Reset Note 1 SINT...
Page 357 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (4) Various signals Figures 16-22 to 16-27 show various signals in the SBI and flag operations of the serial bus interface control register (SBIC). Table 16-5 lists various signals in SBI. Figure 16-22.
Page 358 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-24. ACKT Operation SCK0 SB0 (SB1) ACK signal is output during a period of one clock immediately after setting ACKT When set during this period Caution Do not set ACKT before termination of transfer. www.DataSheet4U.com...
Page 359 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-25. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 SB0 (SB1) ACK signal is output at 9th clock ACKE When ACKE = 1 at this point (b) When set after completion of transfer SCK0 SB0 (SB1)
Page 360 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-26. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 Transfer Start Instruction SIO0 Transfer Start SCK0 SB0 (SB1) ACKD (b) When ACK signal is output after 9th clock of SCK0 Transfer Start Instruction SIO0 Transfer Start...
Page 361 Table 16-5. Various Signals in SBI Mode (1/2) Signal Name Output Definition Timing Chart Output Condition Effects on Flag Meaning of Signal Device Bus release Master SB0 (SB1) rising edge • RELT set • RELD set CMD signal is output to SCK0 “H”...
Page 362 Table 16-5. Various Signals in SBI Mode (2/2) Signal Name Output Definition Timing Chart Output Condition Effects on Flag Meaning of Signal Device Serial clock Master Synchronous clock to When CSIE0 = 1, CSIIF0 set (rising Timing of signal output (SCK0) output address/command/ execution of...
Page 363 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 : Serial clock input/output pin <1> Master : CMOS and push-pull output <2>...
Page 364 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (6) Address match detection method In the SBI mode, a particular slave device can be selected by sending a slave address from the master device. Address match detection is automatically executed by hardware. With the slave address register (SVA), and if the wake-up function specification bit (WUP) = 1, CSIIF0 is set only when the slave address transmitted from the master device matches the value set in SVA.
Page 365 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (8) Communication operation In the SBI mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an “address” to the serial bus. After the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave devices.
Page 366 Figure 16-29. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) Interrupt Servicing Write CMDT RELT CMDT Program Processing (Preparation for the Next Serial Transfer) to SIO0 ACKD SCK0 INTCSI0 Hardware Operation Serial Transmission Generation Stop Transfer Line...
Page 367 Figure 16-30. Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Write Interrupt Servicing CMDT Program Processing to SIO0 (Preparation for the Next Serial Transfer) ACKD SCK0 INTCSI0 Hardware Operation Serial Transmission Generation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY...
Page 368 Figure 16-31. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Interrupt Servicing Write Program Processing (Preparation for the Next Serial Transfer) to SIO0 ACKD SCK0 INTCSI0 Hardware Operation Serial Transmission Generation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY...
Page 369 Figure 16-32. Data Transmission from Slave Device to Master Device Master Device Processing (Receiver) SIO0 ACKT FFH Write FFH Write Receive Data Processing Program Processing to SIO0 Read to SIO0 Serial SCK0 INTCSI0 Hardware Operation Serial Transmission Generation Output Reception Stop Transfer Line SCK0 Pin...
Page 370 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...
Page 371 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (11) Cautions on SBI mode (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used.
Page 372: 2-Wire Serial I/O Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode supports any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Page 373 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Symbol <7> <6> <5> Address When Reset CSIM0 CSIE0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H Note 1 Serial Interface Channel 0 Clock Selection CSIM01 CSIM02 × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) Operating...
Page 374 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 375 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> <3> <2> Address When Reset Note 1 SINT...
Page 376 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 377 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (3) Various signals Figure 16-35 shows RELT and CMDT operations. Figure 16-35. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 378: I 2 C Bus Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.4.5 I C bus mode operation The I C bus mode is used when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line.
Page 379 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (1) I C bus mode functions In the I C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.
Page 380 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) The start condition, slave address, and stop condition signals are output by the master. The acknowledge signal (ACK) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent).
Page 381 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (b) Address The 7 bits following the start condition signal are defined as an address. The 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line.
Page 382 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. The receiving side returns an acknowledge signal each time it receives 8-bit data. The receiving side usually outputs after it receives 8-bit data.
Page 383 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. The slave device notifies the master device about the wait state by keeping the SCL pin low.
Page 384 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (3) Register setting The I C bus mode setting is performed by the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 385 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Wake-up Function Control Note 1 Interrupt request signal generation with each serial transfer in all modes Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1 when the SBI mode is used or when CMDD = 1 when the I C bus mode is used) matches the slave address register (SVA) data in the SBI mode and the I...
Page 386 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2>...
Page 387 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Note 1 ACKE Acknowledge Signal Automatic Output Control (in the I C bus mode) Disables acknowledge signal automatic output. (However, output with ACKT enable) Note 2 Use for reception when 8-clock wait mode is selected or for transmission Enables acknowledge signal automatic output.
Page 388 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> <3> <2> Address When Reset Note 1 SINT...
Page 389 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) SVAM SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 INTCSI0 Interrupt Cause Selection Note 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection in I C bus mode Note 2...
Page 390 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (4) Various signals A list of signals in the I C bus mode is given in Table 16-6. Table 16-6. Signals in the I C Bus Mode Signal name Signaled by Definition Signaled when Affected flag(s)
Page 391 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL ......Pin for serial clock input/output. <1>...
Page 392 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (6) Address match detection method In the I C mode, the master can select a specific slave device by sending slave address data. Address match detection is performed automatically by the slave device hardware. CSIIF0 is set only when a slave device address has a slave register (SVA), the wake-up function specification bit (WUP) is 1, and the slave address sent from the master device matches with the address set in SVA.
Page 393 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-45. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address Master device operation SIO0 ← Address SIO0 ← Address Write SIO0 ACKD CMDD...
Page 394 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-45. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data Master device operation SIO0 ← Data SIO0 ← Data Write SIO0 ACKD CMDD “L”...
Page 395 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-45. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition Master device operation SIO0 ← Address SIO0 ← Address Write SIO0 ACKD CMDD RELD...
Page 396 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-46. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address Master device operation SIO0 ← Address SIO0 ← FFH Write SIO0 ACKD CMDD...
Page 397 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-46. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data Master device operation SIO0 ← FFH SIO0 ← FFH Write SIO0 ACKD CMDD “L”...
Page 398 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) Figure 16-46. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition Master device operation SIO0 ← FFH SIO0 ← Address Write SIO0 ACKD CMDD RELD...
Page 399 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (9) Start of transfer A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied: • The serial interface channel 0 operation control bit (CSIE0) = 1. •...
Page 400: Cautions On Use Of I C Bus Mode
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.4.6 Cautions on use of I C bus mode (1) Start condition output (master) The SCL pin normally outputs the low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal.
Page 401 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (2) Slave wait release (slave transmission) Slave wait release operation is performed by WREL flag (bit 2 of interrupt timing specification register (SINT)) setting or execution of a serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.
Page 402 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (3) Slave wait release (slave reception) Slave wait release operation is performed by WREL flag (bit 2 of interrupt timing specification register (SINT)) setting or execution of a serial I/O shift register 0 (SIO0) write instruction. When the slave receives a data, if the SCL line will immediately become high-impedance state by executing of write instruction to the SIO0, 1st bit data from the master may not be received.
Page 403: Restrictions On Use Of I
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (4) Reception completion processing by a slave During processing of reception completion by a slave device (interrupt servicing etc.), confirm the status of bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of serial operating mode register 0 (CSIM0) (when CMDD = 1).
Page 404 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (2) Restriction on slave device operation in the I C bus mode µ PD78011BY, 78012BY, 78013Y, 78014Y, 78P014Y Applied devices: IE-78014-R-EM Description: If all of the following conditions are satisfied, all slave devices on the transfer line cannot transmit data.
Page 405 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) If the stop condition output timing for the µ PD78014Y Subseries device has been determined Avoidance: previously (i.e. amount of communication data between the µ PD78014Y Subseries device and the master device is fixed), then it is possible to avoid this restriction by software. Set bit 5 (WUP) of serial operating mode register 0 (CSIM0) and serial I/O shift register 0 (SIO0) of the slave device to 1 and FFH respectively before a stop condition signal is output.
Page 406: Sck0/Scl/P27 Pin Output Manipulation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) 16.4.8 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin incorporates an output latch. Therefore, in addition to normal serial clock output, static output from this pin is also possible by controlling the output latch with an instruction. Manipulating the output latch through the software for the P27 pin, the value of serial clock can be selected by software.
Page 407 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) (2) In the I C bus mode The output level of the SCK0/SCL/P27 pin is manipulated by the CLC bit of the interrupt timing specification register (SINT). <1> Set the serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation is enabled).
Page 408 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries) [MEMO] www.DataSheet4U.com...
Page 409: Chapter 17 Serial Interface Channel 1
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode Operation stop mode is used when serial transfer is not carried out.
Page 410: Serial Interface Channel 1 Configuration
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 17-1. Serial Interface Channel 1 Configuration Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Control register Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1)
Page 411 Figure 17-1. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/Receive Buffer RAM Address Pointer (ADTP) Internal Bus Automatic Data Transmit Serial Operating Mode Receive Control Register Register 1 CSIE1 ATE CSIM11 CSIM10 ARLD ERCE ERR STRB BUSY1 BUSY0 Serial I/O Shift SI1/P20 Register 1 (SIO1)
Page 412 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.
Page 413: Serial Interface Channel 1 Control Registers
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17.3 Serial Interface Channel 1 Control Registers The following three types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) •...
Page 414 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-2. Timer Clock Select Register 3 Format Symbol Address When Reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection 2 Note (1.25 MHz) (625 kHz) (313 kHz)
Page 415 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Page 416 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable, and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
Page 417 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-4. Automatic Data Transmit/Receive Control Register Format Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address When Reset Note 1 ADTC ARLD ERCE STRB BUSY1 BUSY0 FF69H BUSY1 BUSY0 Busy Input Control ×...
Page 418: Serial Interface Channel 1 Operations
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.
Page 419: 3-Wire Serial I/O Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface as is the case with the 75X/XL, 78K and 17K series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1).
Page 420 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock (SCK1). The transmit data is held in the SO1 latch and is output from the SO1 pin.
Page 421 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 17-6 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read/written in inverted form.
Page 422: 3-Wire Serial I/O Mode Operation With Automatic Transmit/Receive Function
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 17.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
Page 423 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Symbol <7> <5> Address When Reset CSIM1 CSIE1 CSIM11 CSIM10 FF68H CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection × Note 1 Clock externally input to SCK1 pin 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3) Serial Interface Channel 1 Operating Mode Selection 3-wire serial I/O mode...
Page 424 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address When Reset ADTC ARLD ERCE STRB BUSY1 BUSY0 FF69H Note 1 BUSY1 BUSY0 Busy Input Control × Not using busy input Busy input enable (active high) Busy input enable (active low) STRB Strobe Output Control...
Page 425 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). However, the transmit data should be in the order from high-order address to low-order address. <2>...
Page 426 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer starts when any data is written to the serial I/O shift register 1 (SIO1) while the serial operating mode register 1 (CSIM1) bit 7 (CSIE1) is set to 1.
Page 427 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-8. Basic Transmit/Receive Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer Software Execution value) obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 (start trigger) Write transmit data from buffer RAM to SIO1...
Page 428 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, buffer RAM operates as follows. Before transmission/reception (Refer to Figure 17-9 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
Page 429 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception point FADFH Receive data 1 (R1) Receive data 4 (R4) SIO1 FAC5H Receive data 2 (R2) Receive data 3 (R3) ADTP Transmit data 4 (R4) –1...
Page 430 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer starts when any data is written to the serial I/O shift register 1 (SIO1) while the serial operating mode register 1 (CSIM1) bit 7 (CSIE1) is set to 1.
Page 431 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-11. Basic Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer Software Execution value) obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 (Start trigger) Write transmit data Decrement pointer value...
Page 432 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, buffer RAM operates as follows. Before transmission (Refer to Figure 17-12 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
Page 433 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point FADFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP Transmit data 4 (T4) –1 Transmit data 5 (T5)
Page 434 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer starts by writing any data to the serial I/O shift register 1 (SIO1) when 1 is set in the serial operating mode register 1 (CSIM1) bit 7 (CSIE1).
Page 435 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-14. Repeat Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer Software Execution value) obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 (Start trigger) Write transmit data from buffer Decrement pointer value...
Page 436 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in the repeat transmit mode, buffer RAM operates as follows. Before transmission (Refer to Figure 17-15 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
Page 437 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes FADFH Transmit data 1 (T1) SIO1 FAC5H Transmit data 2 (T2) Transmit data 3 (T3) ADTP Transmit data 4 (T4) Transmit data 5 (T5)
Page 438 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. During 8-bit data transfer, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data transfer.
Page 439 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active.
Page 440 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 Figure 17-18. Operation Timings when Using Busy Control Option (BUSY0 = 0) SCK1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY Wait...
Page 441 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (b) Busy & strobe control option Strobe control is a function to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB/P23 pin when 8-bit transmission/ receptixon has been completed.
Page 442 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte.
Page 443 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (5) Automatic data transmit/receive interval When the automatic data transmit/receive function is used, one byte is transmitted/received and then the read/ write operations from/to the buffer RAM are performed, therefore an interval is inserted before the next data transmission/reception.
Page 444 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (a) In case the automatic data transmit/receive function is performed by an internal clock When bit 1 (CSIM11) of the serial operation mode register 1 (CSIM1) is set to 1, the internal clock performs. In this case, the interval is determined as follows by CPU processing.
Page 445 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 (b) In case the automatic data transmit/receive function is performed by an external clock When bit 1 (CSIM11) of the serial operation mode register 1 (CSIM1) is cleared to 0, the external clock performs. When the automatic data transmit/receive function is performed by an external clock, it must be chosen so that the interval may be longer than the value shown below.
Page 446 CHAPTER 17 SERIAL INTERFACE CHANNEL 1 [MEMO] www.DataSheet4U.com...
Page 447: Chapter 18 Interrupt Functions And Test Function
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests.
Page 448 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Table 18-1. Interrupt Source List Interrupt Type Default Interrupt Source Internal/ Vector Basic Priority Note 1 Name Trigger External Table Configuration Note 2 Address Type Non-maskable — INTWDT Watchdog timer overflow Internal 0004H (with watchdog timer mode 1 selected) Maskable INTWDT...
Page 449 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Vector Table Priority Control Interrupt Address Circuit Request Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus www.DataSheet4U.com Vector Table Priority Control Address...
Page 450 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (INTM0 ) Vector Table Priority Control Address Edge Interrupt Circuit Generator Detector Request Standby Release Signal (E) Software interrupt...
Page 451: Interrupt Function Control Registers
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H) • Interrupt mask flag register (MK0L, MK0H) • Priority specify flag register (PR0L, PR0H) •...
Page 452 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (1) Interrupt request flag registers (IF0L, IF0H) The interrupt request flag is set to (1) when the corresponding interrupt request is generated or an instruction is executed. It is cleared to (0) when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 453 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (2) Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and the standby clear. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are used together as a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction.
Page 454 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (3) Priority specify flag registers (PR0L, PR0H) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. When PR0L and PR0H are used together as a 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
Page 455 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (4) External interrupt mode register (INTM0) This register sets the valid edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Remarks 1. INTP0 is also used for TI0/P00. 2.
Page 456 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction.
Page 457 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION When the sampling INTP0 input level is active twice in succession, the noise eliminator sets the interrupt request flag (PIF0) to 1. Figure18-7 shows noise eliminator input/output timing. Figure 18-7. Noise Eliminator Input/Output Timing (when rising edge is detected) (a) When input is less than the sampling cycle (t Sampling Clock INTP0...
Page 458 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped.
Page 459: Interrupt Servicing Operations
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.4 Interrupt Servicing Operations 18.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents of acknowledged interrupt is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.
Page 460 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-9. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledge Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt request selected)? Reset processing Interrupt request generation WDT interrupt servicing?
Page 461 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-11. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI request <1> NMI request <1> executed. NMI request <2> kept pending. NMI request <2>...
Page 462: Maskable Interrupt Request Acknowledge Operation
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask flag for that interrupt is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
Page 463 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-12. Interrupt Request Acknowledge Processing Algorithm Start ×× IF = 1? Yes (Interrupt Request Generation) ×× MK = 0? Interrupt request reserve Yes (High Priority) ×× PR = 0? No (Low Priority) Any high- priority interrupt among simultaneously...
Page 464 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-13. Interrupt Request Acknowledge Timing (Minimum Time) 12 Clocks PSW, PC Save, Jump Interrupt Servicing CPU Processing Instruction Instruction to Interrupt Servicing Program ×× ×× PR = 1) 15 Clocks ×× ×× PR = 0) 13 Clocks Remark...
Page 465: Software Interrupt Request Acknowledge Operation
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt request cannot be disabled. If a software interrupt request is acknowledged, it is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into PC and branched.
Page 466 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-15. Multiple Interrupt Examples (1/2) Example 1. Two multiple interrupts are generated Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE = 0 IE = 0 IE = 0 INTyy INTzz INTxx (PR = 0) (PR = 0) (PR = 1)
Page 467 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Figure 18-15. Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupts are not enabled Main Processing INTxx INTyy Servicing Servicing IE = 0 INTyy INTxx (PR = 0) (PR = 0) RETI IE = 0...
Page 468: Interrupt Request Reserve
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution. The following shows such instructions (interrupt request reserve instruction).
Page 469: Test Function
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 18.5 Test Function In this function, when the watch timer overflows and when a rising edge of port 4 is detected, the corresponding test input flag is set (1), and a standby release signal is generated. Unlike the interrupt function, vectored processing not performed.
Page 470 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION Names of test input flag and test mask flag corresponding to test input signal name are shown in Table 18-6. Table 18-6. Various Flags Corresponding to Test Input Signal Test Input Signal Name Test Input Flag Test Mask Flag INTWT...
Page 471: Test Input Signal Acknowledge Operation
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION (3) Key return mode register (KRM) This register set the standby mode clear enable/disable with the key return signal (falling edge detection of Port KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Page 472 CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION [MEMO] www.DataSheet4U.com...
Page 473: Chapter 19 External Device Expansion Function
CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION 19.1 External Device Expansion Functions The external device expansion functions are intended to connect external devices to areas other than the internal ROM, RAM and SFR. Connection of external devices uses port 4 to port 6. Port 4 to port 6 control address/data, read/write strobe, wait, address strobe, etc.
Page 474 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 19-1. Memory Map when Using External Device Expansion Function (1/2) (a) µ PD78011B, 78011BY Memory Map (b) µ PD78012B, 78012BY Memory Map F F F F H F F F F H F F 0 0 H...
Page 475 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION Figure 19-1. Memory Map when Using External Device Expansion Function (2/2) (a) µ PD78013, 78013Y Memory Map (b) µ PD78014, 78014Y, 78P014, 78P014Y Memory Map F F F F H F F F F H F F 0 0 H F F 0 0 H F E F F H...
Page 476: External Device Expansion Control Register
CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION 19.2 External Device Expansion Control Register The external device expansion function is controlled by the memory expansion mode register (MM). MM sets the wait count and external expansion area. MM also sets the input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction.
Page 477: External Device Expansion Function Timing
CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION 19.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data access and instruction fetch from external memory.
Page 478 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION Figure 19-3. Instruction Fetch from External Memory (a) When without Wait (PW1, PW0 = 0, 0) Setup ASTB Low-order AD0 to AD7 Instruction code address A8 to A15 High-order address (b) When with Wait (PW1, PW0 = 0, 1) Setup ASTB Low-order AD0 to AD7...
Page 479 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION Figure 19-4. External Memory Read Timing (a) When without Wait (PW1, PW0 = 0, 0) Setup ASTB Low-order AD0 to AD7 Read data address High-order address A8 to A15 (b) When with Wait (PW1, PW0 = 0, 1) Setup ASTB Low-order AD0 to AD7...
Page 480 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION Figure 19-5. External Memory Write Timing (a) When without Wait (PW1, PW0 = 0, 0) Setup ASTB Hi-Z Low-order AD0 to AD7 Write data address A8 to A15 High-order address (b) When with Wait (PW1, PW0 = 0, 1) Setup ASTB Hi-Z Low-order...
Page 481 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION Figure 19-6. External Memory Read Modify Write Timing (a) When without Wait (PW1, PW0 = 0, 0) Setup ASTB Low-order AD0 to AD7 Read data Write data address A8 to A15 High-order address (b) When with Wait (PW1, PW0 = 0, 1) Setup ASTB Low-order AD0 to AD7...
Page 482: Example Of Memory Connection
CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION 19.4 Example of Memory Connection An example of external memory connection with the µ PD78014 is shown in Figure 19-7. SRAM is used as the external memory in this application example. In addition, the external device expansion function is used in the full- address mode, and the internal ROM is allocated to addresses 0000H to 7FFFH (32 Kbytes), and SRAM is allocated to addresses above 8000H.
Page 483: Chapter 20 Standby Function
CHAPTER 20 STANDBY FUNCTION CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is intended to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation.
Page 484: Standby Function Control Register
CHAPTER 20 STANDBY FUNCTION 20.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 485: Standby Function Operations
CHAPTER 20 STANDBY FUNCTION 20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below.
Page 486 CHAPTER 20 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request The HALT mode is cleared when the unmasked interrupt request is generated. If interrupt request acknowledge is enabled, vectored interrupt service is carried out.
Page 487 CHAPTER 20 STANDBY FUNCTION (d) Clear upon RESET input The HALT mode is cleared when the RESET signal inputs. As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 20-3. HALT Mode Clear upon RESET Input Wait HALT : 26.2 ms)
Page 488: Stop Mode
CHAPTER 20 STANDBY FUNCTION 20.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, X1 input is internally short-circuited to V (ground potential) to suppress the leakage at the crystal oscillator.
Page 489 CHAPTER 20 STANDBY FUNCTION (2) STOP mode clear The STOP mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request The STOP mode is cleared when the unmasked interrupt request is generated. If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 490 CHAPTER 20 STANDBY FUNCTION (c) Clear upon RESET input The STOP mode is cleared when the RESET signal inputs and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 20-5. STOP Mode Clear upon RESET Input Wait : 26.2 ms) STOP...
Page 491: Chapter 21 Reset Function
CHAPTER 21 RESET FUNCTION CHAPTER 21 RESET FUNCTION 21.1 Reset Function The following two operations are available to generate the reset function. (1) External reset input with RESET pin (2) Internal reset by watchdog timer inadvertent program loop time detection External reset and internal reset have no functional differences.
Page 492 CHAPTER 21 RESET FUNCTION Figure 21-2. Timing of Reset by RESET Input Oscillation Normal Operation Reset Period Stabilization Normal Operation (Oscillation Stop) (Reset Processing) Time Wait RESET Internal Reset Signal Delay Delay High-Impedance Port Pin Figure 21-3. Timing of Reset due to Watchdog Timer Overflow Normal Operation Reset Period Oscillation...
Page 493 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (1/2) Hardware Status after Reset Program counter (PC) Note 1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Data memory Undefined Note 2 General register...
Page 494 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (2/2) Hardware Status after Reset Watch timer Mode control register (TMC2) Clock select register (TCL2) Watchdog timer Mode register (WDTM) Serial interface Clock select register (TCL3) Shift registers (SIO0, SIO1) Undefined Mode registers (CSIM0, CSIM1) Serial bus interface control register (SBIC)
Page 495: Chapter 22 Μ Pd78P014, 78P014Y
CHAPTER 22 µ PD78P014, 78P014Y CHAPTER 22 µ PD78P014, 78P014Y The µ PD78P014 and 78P014Y are versions which incorporate a one-time programmable PROM or an EPROM enabled for program write, erase and rewrite. Table 22-1 lists differences between µ PD78P014, 78P014Y and mask ROM version.
Page 496 CHAPTER 22 µ PD78P014, 78P014Y Figure 22-1. Internal Memory Size Switching Register Format Symbol Address When Reset RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 FFF0H Note ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection 4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Other than above...
Page 497: Prom Programming
CHAPTER 22 µ PD78P014, 78P014Y 22.2 PROM Programming The µ PD78P014 and 78P014Y incorporate a 32K-byte PROM as program memory. When programming the µ PD78P014 and 78P014Y, the PROM programming mode is set by means of the V pin and the RESET pin. For the connection of unused pins, see 1.5 or 2.5 Pin Configurations (Top View), (2) PROM programming mode.
Page 498: Prom Write Procedure
CHAPTER 22 µ PD78P014, 78P014Y 22.2.2 PROM write procedure PROM contents can be written using the following procedure and high-speed writing is enabled. (1) Fix the RESET pin low, and supply +5 V to the V pin. Unused pins are handled as shown in 1.5 or 2.5 Pin Configuration, (Top View), (2) PROM programming mode.
Page 499 CHAPTER 22 µ PD78P014, 78P014Y Figure 22-3. Write Procedure Flowchart Start Supply Power Voltage Supply Initial Address Supply Write Data Supply Program Pulse Write disabled Write disabled (25th time) (Less than 25 times) Verify Mode Write OK www.DataSheet4U.com Additional Write (3Xms pulse) X: Write repeat times Increment Address (10)
Page 500: Prom Read Procedure
CHAPTER 22 µ PD78P014, 78P014Y 22.2.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V pin. Unused pins are handled as shown in 1.5 or 2.5 Pin Configurations (Top View), (2) PROM programming mode.
Page 501: Erasure Characteristics (For Μ Pd78P014Dw, 78P014Ydw)
Because of their construction, one-time PROM versions ( µ PD78P014CW, 78P014YCW, 78P014GC-AB8, 78P014YGC- AB8) cannot be fully tested by NEC before shipment. After the necessary data has been written, it is recommended that screening is implemented in which PROM verification is performed after high-temperature storage under the following conditions.
Page 502 CHAPTER 22 µ PD78P014, 78P014Y [MEMO] www.DataSheet4U.com...
Page 503: Chapter 23 Instruction Set
CHAPTER 23 INSTRUCTION SET CHAPTER 23 INSTRUCTION SET The instruction sets for the µ PD78014 and 78014Y Subseries are described in the following pages. For the details of operations and mnemonics (instruction codes) of each instruction, refer to the 78K/0 Series User’s Manual, Instructions (U12326E).
Page 504: Legend
CHAPTER 23 INSTRUCTION SET 23.1 Legend 23.1.1 Operand identifiers and description methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
Page 505: Description Of "Operation" Column
CHAPTER 23 INSTRUCTION SET 23.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 506: Operation List
CHAPTER 23 INSTRUCTION SET 23.2 Operation List Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group r ← byte 8-bit r, #byte — (saddr) ← byte data saddr, #byte sfr ← byte trans- sfr, #byte —...
Page 507 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group A ↔ r Note 3 8-bit A, r — A ↔ (saddr) data A, saddr A ↔ sfr trans- A, sfr —...
Page 508 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group A, CY ← A+byte × × × 8-bit A, #byte — (saddr), CY ← (saddr)+byte × × × Ope- saddr, #byte A, CY ←...
Page 509 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group A, CY ← A–byte–CY × × × 8-bit SUBC A, #byte — (saddr), CY ← (saddr)–byte–CY × × × Ope- saddr, #byte A, CY ←...
Page 510 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group A ← A ∨ byte × 8-bit A, #byte — (saddr) ← (saddr) ∨ byte × Ope- saddr, #byte A ← A ∨ r ×...
Page 511 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group r ← r+1 × × Increase/ INC — (saddr) ← (saddr)+1 × × Decrease saddr r ← r–1 × × — (saddr) ←...
Page 512 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 Z AC CY Group CY ← CY∧ (saddr.bit) × AND1 CY, saddr.bit CY ← CY∧ sfr.bit × Manipu- CY, sfr.bit — CY ← CY∧ A.bit ×...
Page 513 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 Z AC CY Group (SP–1) ← (PC+3) , (SP–2) ← (PC+3) Call CALL !addr16 — PC ← addr16, SP ← SP–2 Return (SP–1) ← (PC+2) , (SP–2) ←...
Page 514 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 Z AC CY Group PC ← addr16 Uncon- BR !addr16 — PC ← PC + 2 + jdisp8 ditional $addr16 — ← A, PC ←...
Page 515 CHAPTER 23 INSTRUCTION SET Instruc- Mnemonic Operands Byte Clock Operation Flag tion Note 1 Note 2 AC CY Group B ← B–1, then Condi- DBNZ B, $addr16 — PC ← PC + 2 + jdisp8 if B ≠ 0 tional C ←...
Page 516: Instructions Listed By Addressing Type
CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ www.DataSheet4U.com...
Page 517 CHAPTER 23 INSTRUCTION SET Second #byte Note saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 None Operand [HL+B] First [HL+C] Operand ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C DBNZ www.DataSheet4U.com saddr DBNZ ADDC...
Page 518 CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word Note sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW MOVW MOVW Note INCW DECW PUSH sfrp MOVW...
Page 519 CHAPTER 23 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP www.DataSheet4U.com...
Page 520 CHAPTER 23 INSTRUCTION SET [MEMO] www.DataSheet4U.com...
Page 521: And 78018F Subseries
APPENDIX A DIFFERENCES BETWEEN µ PD78014, 78014H, AND 78018F SUBSERIES APPENDIX A DIFFERENCES BETWEEN µ PD78014, 78014H, AND 78018F SUBSERIES Table A-1 shows the major differences between the µ PD78014, 78014H, and 78018F Subseries. Table A-1. Major Differences between µ PD78014, 78014H, and 78018F Subseries (1/2) Part Number µ...
Page 522 APPENDIX A DIFFERENCES BETWEEN µ PD78014, 78014H, AND 78018F SUBSERIES Table A-1. Major Differences between µ PD78014, 78014H, and 78018F Subseries (2/2) Part Number µ PD78014 Subseries µ PD78014H Subseries µ PD78018F Subseries Item Function of bit 7 (BSYE) of Control of synchronous bus —...
Page 523: Appendix B Development Tools
APPENDIX B DEVELOPMENT TOOLS APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78014 and 78014Y Subseries. Figure B-1 shows the development tools configuration. www.DataSheet4U.com...
Page 524 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tools Configuration Embedded software PROM programmer control software • Real-time OS, OS • PG-1500 controller • Fuzzy inference development support system Language processing software • Assembler package • C compiler package • C library source file •...
Page 525: Language Processing Software
APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 This is a program to convert a program written in mnemonics into an object code executable with Assembler Package a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization.
Page 526: Prom Programming Tools
APPENDIX B DEVELOPMENT TOOLS B.2 PROM Programming Tools B.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller’s PROM programmer on-chip PROM by manipulating from the stand-alone or host machine through connection of a programmer adapter separately purchasable and the supplied board. It can also program typical PROMs the capacities of which range from 256 Kbits to 4 Mbits.
Page 527: Debugging Tools
APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tools B.3.1 Hardware IE-78000-R-A This is the in-circuit emulator for debugging hardware and/or software when a system is In-circuit emulator developed with 78K/0 Series devices. This emulator is designed to be used with the (For integrated debugger) integrated debugger (ID78K0).
Page 528: Software
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/3) SM78K0 It is possible to debug at C source level or assembler level while simulating target system on the System simulator host machine. SM78K0 runs on Windows. By using SM78K0, logic and performance verification of application without in-circuit emulator is possible independently of hardware development, and development efficiency and software quality will thus be improved.
Page 529 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/3) ID78K0 This debugger is a control program used to debug applications of the 78K/0 Series devices. This Integrated debugger software has a Windows-based (PC version) or OSF/Motif -based (EWS version) graphical user interface to provide comfortable operation environments. It also has an enhanced debugging function for C language support, and it is possible to display trace results at the C-language level by using its window integration feature which links source programs, disassembled display, and memory content display to their trace results.
Page 530 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (3/3) SD78K/0 The IE-78000-R is controlled in the host machine through connection with the host machine and Screen debugger IE-78000-R via serial interface (RS-232-C). This is used together with the separately sold device file (DF78014). Part Number: µ...
Page 531: Os For Ibm Pc
APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs for IBM PC are supported. When operating SM78K0, ID78K0, FE9200 (See C.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary. Version PC DOS Ver.
Page 532: System-Up Method From Other In-Circuit Emulator To In-Circuit Emulator For The 78K/0 Series
IE-78330-R, IE-78350-R 78K/0 Series IE-78000-R — Note 2 Notes 1. Available for maintenance purposes only. 2. It is needed to take out to NEC to change a part of in-circuit emulator and replace the control/trace board with the supervisor board...
Page 533 APPENDIX B DEVELOPMENT TOOLS Package Drawing and Footprint of Conversion Socket (EV-9200GC-64) Figure B-2. EV-9200GC-64 Package Drawing (for reference only) EV-9200GC-64 No.1 pin index EV-9200GC-64-G0 ITEM MILLIMETERS INCHES www.DataSheet4U.com 18.8 0.74 14.1 0.555 14.1 0.555 18.8 0.74 4-C 3.0 4-C 0.118 0.031 0.236 15.8...
Page 534 APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-64 Footprint (for reference only) EV-9200GC-64-P1 ITEM MILLIMETERS INCHES 19.5 0.768 14.8 0.583 0.8 ± 0.02 × 15=12.0 ± 0.05 × 0.591=0.472 +0.002 +0.003 0.031 –0.001 –0.002 0.8 ± 0.02 × 15=12.0 ± 0.05 ×...
Page 535: Appendix C Embedded Software
APPENDIX C EMBEDDED SOFTWARE APPENDIX C EMBEDDED SOFTWARE The following embedded software are available for efficient program development and maintenance of the µ PD78014 and 78014Y Subseries. www.DataSheet4U.com...
Page 536: Real-Time Os
APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (1/2) Real-time OS which is based on the µ ITRON specification. RX78K/0 Real-time OS Supplied with the RX78K/0 nucleus and a tool to prepare multiple information tables (configurator). Used in combination with RA78K/0 assembler package (option) and device file (DF78014) (option). Part Number: µ...
Page 537 APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (2/2) MX78K0 is a subset OS which is based on the µ ITRON specification. Supplied with the MX78K0 MX78K0 nucleus. MX78K0 OS controls tasks, events, and time. In task control, MX78K0 OS controls task execution order, and then perform the switching process to a task to be executed.
Page 538: Fuzzy Inference Development Support System
APPENDIX C EMBEDDED SOFTWARE C.2 Fuzzy Inference Development Support System FE9000/FE9200 Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing Fuzzy Knowledge Data (edit), and evaluation (simulation). Preparation Tool FE9200 operates on Windows. Part Number: µ S××××FE9000 (PC-9800 series) µ...
Page 539: Appendix D Register Index
APPENDIX D REGISTER INDEX APPENDIX D REGISTER INDEX D.1 Register Index (In Alphabetical Order with Respect to the Register Name) A/D conversion result register (ADCR) ... 249 A/D converter input select register (ADIS) ... 253 A/D converter mode register (ADM) ... 251 Automatic data transmit/receive address pointer (ADTP) ...
Page 540 APPENDIX D REGISTER INDEX Port mode register 3 (PM3) ... 146, 183, 211, 242, 246 Port mode register 5 (PM5) ... 146 Port mode register 6 (PM6) ... 146 Priority specify flag register 0H (PR0H) ... 454 Priority specify flag register 0L (PR0L) ... 454 Processor clock control register (PCC) ...
Page 541: Register Index (In Alphabetical Order With Respect To The Register Symbol)
APPENDIX D REGISTER INDEX D.2 Register Index (In Alphabetical Order with Respect to the Register Symbol) ADCR A/D conversion result register ... 249 ADIS A/D converter input select register ... 253 A/D converter mode register ... 251 ADTC Automatic data transmit/receive control register ... 416, 423 ADTP Automatic data transmit/receive address pointer ...
Page 542 APPENDIX D REGISTER INDEX Port mode register 6 ... 146 PR0H Priority specify flag register 0H ... 454 PR0L Priority specify flag register 0L ... 454 Program status word ... 102, 458 Pull-up resistor option register ··· 149 SBIC Serial bus interface control register ... 274, 280, 293, 313, 330, 341, 354, 374, 386 Sampling clock select register ...
Page 543: Appendix E Revision History
APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. (1/4) Edition Major revisions from previous edition Revised Chapters µ PD78014Y subseries were added as applied devices. General Frequency of main system clock oscillator is changed from 8.38 MHz to 10.0 MHz. Item “After Reset”...
Page 544 APPENDIX E REVISION HISTORY (2/4) Edition Major revisions from previous edition Revised Chapters Format of the A/D converter mode register was changed. CHAPTER 12 Section 12.4.2 “Input voltage and conversion results” was added. A/D CONVERTER Following items were added in section 12.5 “Cautions on A/D Converter”. (5) AV pin input impedance (6) Interrupt request flag of A/D conversion end (INTAD)
Page 545 APPENDIX E REVISION HISTORY (3/4) Edition Major revisions from previous edition Revised Chapters µ PD78011B(A), 78012B(A), 78013(A), 78014(A) were added as applied devices. General Cautions on rewriting the timer clock select registers 0 to 2 (TCL0 to TCL2) to other data was added. Watchdog timer count clocks (Inadvertent program loop detection period) selected by TCL20 to TCL22 of the timer clock select register 2 (TCL2) were changed.
Page 546 APPENDIX E REVISION HISTORY (4/4) Edition Major revisions from previous edition Revised Chapters P20, P21, P23 to P26 Block Diagrams, P22 and P27 Block Diagrams, and P30 to CHAPTER 6 P37 Block Diagrams were corrected. PORT FUNCTIONS Figure 9-10 and 9-13, “Square Wave Output Operation Timings” were added. CHAPTER 9 8-BIT TIMER/EVENT COUNTER...
Page 547 APPENDIX E REVISION HISTORY Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and...

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NEC 78014Y Series User Manual

CHAPTER 1 OUTLINE ( Μ PD78014 Subseries)

Features

Application Fields

Ordering Information

Quality Grade

Pin Configurations (Top View)

Series Expansion

Block Diagram

Outline of Function

Differences Among Μ PD78011B, 78012B, 78013, 78014 and Μ PD78011B(A), 78012B(A), 78013(A), 78014(A)

Mask Options

CHAPTER 2 OUTLINE ( Μ PD78014Y Subseries)

Features

Application Fields

Ordering Information

Quality Grade

Pin Configurations (Top View)

Series Expansion

Block Diagram

Outline of Function

Mask Options

CHAPTER 3 PIN FUNCTION ( Μ PD78014 Subseries)

Pin Function List

Description of Pin Functions

Input/Output Circuit and Recommended Connection of Unused Pins

CHAPTER 4 PIN FUNCTION ( Μ PD78014Y Subseries)

Pin Function List

Description of Pin Functions

Input/Output Circuit and Recommended Connection of Unused Pins

Chapter 5 Cpu Architecture

Memory Spaces

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 6 Port Functions

Port Block Diagram

Port Function Control Registers

Port Function Operations

Mask Options

Chapter 7 Clock Generator

Clock Generator Functions

Clock Generator Configuration

Clock Generator Control Register

System Clock Oscillator

Clock Generator Operations

Changing System Clock and CPU Clock Settings

Chapter 8 16-Bit Timer/Event Counter

Outline of On-Chip Timer in Μ PD78014, 78014Y Subseries

16-Bit Timer/Event Counter Functions

16-Bit Timer/Event Counter Configuration

16-Bit Timer/Event Counter Control Registers

16-Bit Timer/Event Counter Operations

16-Bit Timer/Event Counter Operating Precautions

Chapter 9 8-Bit Timer/Event Counter

8-Bit Timer/Event Counter Functions

8-Bit Timer/Event Counter Configuration

8-Bit Timer/Event Counter Control Registers

8-Bit Timer/Event Counter Operations

Cautions on 8-Bit Timer/Event Counter Operating

Chapter 10 Watch Timer

Watch Timer Functions

Watch Timer Configuration

Watch Timer Control Registers

Watch Timer Operations

Chapter 11 Watchdog Timer

Watchdog Timer Functions

Watchdog Timer Configuration

Watchdog Timer Control Registers

Watchdog Timer Operations

Chapter 12 Clock Output Control Circuit

Clock Output Control Circuit Functions

Clock Output Function Control Registers

Clock Output Control Circuit Configuration

Chapter 13 Buzzer Output Control Circuit

Buzzer Output Control Circuit Functions

Buzzer Output Control Circuit Configuration

Buzzer Output Function Control Registers

Chapter 14 A/D Converter

A/D Converter Functions