Chip-Select Flash Write Cycle Timing; Table 19-5 Chip-Select Write Cycle Timing Parameters - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
Table 19-5. Chip-Select Write Cycle Timing Parameters
Number
1 Address valid to CSx asserted
(bit ECDS = 0, bit ECDS = 1)
2 CSx asserted to UWE/LWE asserted
3 CSx asserted to data-out valid
4 External DTACK input setup from CSx asserted
5 CSx pulse width
(bit ECDS = 0, bit ECDS = 1)
6 UWE/LWE negated before CSx is negated
7 External DTACK input hold after CSx is negated
8 Data-out hold after CSx is negated
9 CSx negated to data-out in Hi-Z
10 CSx asserted to WE asserted (16-bit SRAM)
11 WE negated before CSx is negated (16-bit SRAM)
Note:
n is the number of wait-states in the current memory access cycle.
T is the system clock period.
The external DTACK input requirement is eliminated when CSx is programmed to use the internal DTACK.
CSx stands for CSA0, CSA1, CSB0, CSB1, CSC0, CSC1, CSD0, or CSD1.
A value in parentheses is used when early detection is turned on.
19.3.4

Chip-Select Flash Write Cycle Timing

Figure 19-4 on page 19-7 shows the flash write cycle timing used by chip-select. The signal values and
units of measure for this figure are found in Table 19-6 on page 19-7. For detailed information about the
individual signals, see Chapter 6, "Chip-Select Logic."
19-6
Characteristic
MC68VZ328 User's Manual
(3.0 ± 0.3) V
Minimum Maximum
20, 20 - T/2 —
0 4
— 30
— 20 + nT
60 + nT, —
(60 + T/2) + nT
10 20
0 —
8 —
— 18
0 4
10 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns