Spi 1 Control/Status Register; Table 13-3 Spi 1 Control/Status Register Description - Motorola MC68VZ328 User Manual

SPI 1 Programming Model
13.3.3

SPI 1 Control/Status Register

This register controls the configuration and operation of the SPI 1 module. The bit position assignments for
this register are shown in the following register display. The settings for this register are described in
Table 13-3.
SPICONT1
BIT
14 13
15
DATA RATE
TYPE rw rw rw
0 0 0
RESET
Table 13-3. SPI 1 Control/Status Register Description
Name
DATA RATE Data Rate—This field selects the bit rate of the
Bits 15–13 SCLK based on the division of the system
clock. The master clock for SPI 1 in master
mode is SYSCLK.
DRCTL DATA_READY Control—In master mode,
Bits 12–11 these 2 bits select the waveform of the
DATA_READY input signal. In slave mode,
they have no effect.
MODE SPI 1 Mode Select—This bit selects the mode
Bit 10 of SPI 1.
SPIEN SPI 1 Enable—This bit enables SPI 1. This bit
Bit 9 must be asserted before initiating an
exchange. Writing a 0 to this bit flushes the Rx
and Tx FIFOs.
XCH Exchange—In master mode, writing a 1 to this
Bit 8 bit triggers a data exchange. This bit remains
set while either the exchange is in progress or
SPI 1 is waiting for active DATA_READY input
while DATA_READY is enabled. This bit is
cleared automatically when all data in the
TxFIFO and shift registers are shifted out. In
slave mode, this bit must be clear.
SSPOL SS Polarity Select—In both master and slave
Bit 7 modes, this bit selects the polarity of SS signal.
13-6
SPI 1 Control/Status Register
12 11 10 9
DRCTL MODE SPIEN
rw rw rw rw
0 0 0 0
Description
MC68VZ328 User's Manual
8 7 6 5
SS SS
XCH PHA
POL CTL
rw rw rw rw
0 0 0 0
0x0000
000 = Divide SYSCLK by 4
001 = Divide SYSCLK by 8
010 = Divide SYSCLK by 16
011 = Divide SYSCLK by 32
100 = Divide SYSCLK by 64
101 = Divide SYSCLK by 128
110 = Divide SYSCLK by 256
111 = Divide SYSCLK by 512
00 = Don't care DATA_READY
01 = Falling edge trigger input
10 = Active low level trigger input
11 = RSV
0 = SPI 1 is slave mode
1 = SPI 1 is master mode
0 = Serial peripheral interface is disabled
1 = Serial peripheral interface is enabled
1 = Initiates exchange (write) or busy (read)
0 = Idle
0 = Active low
1 = Active high
0x(FF)FFF704
BIT
4 3 2 1
0
POL BIT COUNT
rw rw rw rw rw
0 0 0 0 0
Setting