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Table 10-43. Port J Dedicated I/O Function Assignments (Continued)
Bit
7
Bits 0–3 are control signals connected to SPI 1. Their operation is detailed in Section 13.2.4, "SPI 1
Signals," on page 13-3. The remaining 4 bits are control signals for UART 2; more information appears in
Section 14.2.3, "Serial Interface Signals," on page 14-3.
10.4.9.4
Port J Pull-up Enable Register
The pull-up enable register (PJPUEN) controls the pull-up resistors for each line in Port J. The bit settings
for the PJPUEN register are shown in Table 10-44.
PJPUEN
BIT 7
PU7
TYPE
RESET
Table 10-44. Port J Pull-up Enable Register Description
Name
PUx
Pull-up—These bits enable the pull-up resis-
Bits 7–0
tors on the port
10.4.9.5
Port J Select Register
The select register (PJSEL) determines if a bit position in the data register (PJDATA) is assigned as a
GPIO or to a dedicated I/O function. The bit settings for the PJSEL register are shown in Table 10-45.
PJSEL
BIT 7
SEL7
TYPE
RESET
Name
SELx
Select—These bits select whether the internal chip
Bits 7–0
function or I/O port signals are connected to the pins.
GPIO Function
Port J Pull-up Enable Register
6
5
PU6
PU5
rw
rw
rw
1
1
1
Description
Port J Select Register
6
5
SEL6
SEL5
rw
rw
rw
1
1
1
Table 10-45. Port J Select Register Description
Description
I/O Ports
Dedicated I/O Function
Data bit 7
4
3
PU4
PU3
rw
rw
1
1
0xFF
0 = Pull-up resistors are disabled
1 = Pull-up resistors are enabled
4
3
SEL4
SEL3
rw
rw
0
1
0xEF
0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.
Programming Model
CTS2
0x(FF)FFF43A
2
1
BIT 0
PU2
PU1
PU0
rw
rw
rw
1
1
1
Setting
0x(FF)FFF43B
2
1
BIT 0
SEL2
SEL1
SEL0
rw
rw
rw
1
1
1
Setting
10-33
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