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Programming Model
8.3.17
LCD Gray Palette Mapping Register
For four-level grayscale displays, full black and full white are the two predefined display levels. The other
two intermediate grayscale shading densities can be adjusted in the LCD gray palette mapping register
(LGPMR). The bit assignments for the register are shown in the following register display. The settings for
the bits in the register are listed in Table 8-17.
LGPMR
BIT 7
G23
TYPE
rw
1
RESET
Table 8-17. LCD Gray Palette Mapping Register Description
Name
G23–G20
Grayscale 23–20—These bits represent one of the two gray-
Bits 7–4
scale shading densities.
G13–G10
Grayscale 13–10—These bits represent the other grayscale
Bits 3–0
shading density.
8.3.18
PWM Contrast Control Register
The pulse-width modulator contrast control register (PWMR) is used to control the PWMO signal, which
adjusts the contrast of the LCD panel. The bit assignments for the register are shown in the following
register display. The settings for the bits in the register are listed in Table 8-18.
PWMR
BIT
14
13
15
TYPE
0
0
0
RESET
Table 8-18. PWM Contrast Control Register Description
Name
Reserved
Reserved
Bits 15–11
SRC1–0
Source 1–0—These bits select the input clock source for the
Bits 10–9
PWM counter. The PWM output frequency is equal to the fre-
quency of the input clock divided by 256.
8-20
LCD Gray Palette Mapping Register
6
5
G22
G21
rw
rw
0
0
Description
PWM Contrast Control Register
12
11
10
9
CCPE
SRC1–0
rw
rw
0
0
0
0
Description
MC68VZ328 User's Manual
4
3
G20
G13
G12
rw
rw
rw
0
0
0x84
See description
See description
8
7
6
5
PW
PW
PW
N
7
6
5
rw
rw
rw
rw
0
0
0
0
0x0000
These bits are reserved and should
be set to 0.
00 = Line pulse.
01 = Pixel clock.
10 = LCD clock.
11 = Reserved.
0x(FF)FFFA33
2
1
BIT 0
G11
G10
rw
rw
1
0
0
Setting
0x(FF)FFFA36
4
3
2
1
PW
PW
PW
PW
4
3
2
1
rw
rw
rw
rw
0
0
0
0
Setting
BIT
0
PW
0
rw
0
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