In-Circuit Emulation Module Status Register; Typical Design Programming Example; Table 16-6 Ice Module Status Register Description - Motorola MC68VZ328 User Manual

Motorola mc68vz328 integrated processor user's manual
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Typical Design Programming Example

16.2.4

In-Circuit Emulation Module Status Register

The in-circuit emulation module status register (ICEMSR) is used to determine the source of an interrupt.
The bit assignments for the ICE module status register are shown in the following register display. The
settings for the bits are described in Table 16-6.
ICEMSR
BIT 15
14
TYPE
0
0
RESET
Name
Reserved
Reserved
Bits 15–4
EMUEN
Emulation Enable—This bit, when set, enables ICE
Bit 3
mode.
BBIRQ
Bus Break Interrupt Detected—This bit is set when a
Bit 2
bus breakpoint is hit. Writing a 1 to this bit clears it.
BRKIRQ
Line Vector Fetch Detected—This bit is set when a pro-
Bit 1
gram breakpoint is hit. Writing a 1 to this bit clears it.
EMIRQ
EMUIRQ Falling Edge Detected—This bit is set when
Bit 0
the EMUIRQ pin is going from high to low. Writing a 1 to
this bit clears it.
16.3
Typical Design Programming Example
Figure 16-2 on page 16-11 illustrates an example of a typical emulator design. It is a simple and low-cost
design that uses the MC68VZ328 as the processor to be emulated. Other functional units include the host
control to the PC or workstation via an RS-232 or a dedicated parallel interface, an optional address
comparator for extra breakpoint expansion, optional map FPGA for emulation memory remapping, a data
bus MUX for hardware breakpoint insertion, and a MC68VZ328 pin-out extension to connect to the
solder-on emulator pod. The entire MC68VZ328 bus should be buffered using level-shifting buffers when
the emulator is designed in 5 V and the processor is running at 3.3 V.
16-10
ICE Module Status Register
13
12
11
10
9
0
0
0
0
0
Table 16-6. ICE Module Status Register Description
Description
MC68VZ328 User's Manual
8
7
6
5
4
3
EMUEN
rw
0
0
0
0
0
0
0x0000
These bits are reserved and should be
set to 0.
0 = Normal mode.
1 = ICE mode.
0 = Bus breakpoint has not occurred.
1 = Bus breakpoint has occurred.
0 = Program breakpoint has not
occurred.
1 = Program breakpoint has occurred.
See description.
0x(FF)FFFFFD0E
2
1
BIT 0
BBIRQ
BRKIRQ
EMIRQ
rw
rw
rw
0
0
0
Setting

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