Spi 1 Interrupt Control/Status Register; Table 13-4 Spi 1 Interrupt Control/Status Register Description - Motorola MC68VZ328 User Manual

SPI 1 Programming Model
13.3.4

SPI 1 Interrupt Control/Status Register

This register is used to provide interrupt control and status of various operations in SPI 1. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 13-4.
SPIINTCS
BIT
14
15
BO RO RFE
EN EN
TYPE rw rw
0 0
RESET
Table 13-4. SPI 1 Interrupt Control/Status Register Description
Name
BOEN Bit Count Overflow Interrupt Enable—This bit,
Bit 15 when set, allows an interrupt to be generated
when an overflow bit count condition exists. See
the description of the BO (bit 7) for details.
ROEN RxFIFO Overflow Interrupt Enable—This bit,
Bit 14 when set, allows an interrupt to be generated
when an overflow occurs in the RxFIFO. See the
description of the RO (bit 6) for details.
RFEN RxFIFO Full Interrupt Enable—This bit, when
Bit 13 set, allows an interrupt to be generated when
there are 8 data words in the RxFIFO. See the
description of the RF (bit 5) for details.
RHEN RxFIFO Half Interrupt Enable—This bit, when
Bit 12 set, allows an interrupt to be generated when the
contents of the RxFIFO is more than or equal to
4 data words. See the description of the RH (bit
4) for details.
RREN RxFIFO Data Ready Interrupt Enable—This
Bit 11 bit, when set, allows an interrupt to be generated
when at least 1 data word is ready in the
RxFIFO. See the description of the RR (bit 3) for
details.
TFEN TxFIFO Full Interrupt Enable—This bit, when
Bit 10 set, causes an interrupt to be generated when
the TxFIFO buffer is full and the RFEN bit is set.
THEN TxFIFO Half Interrupt Enable—This bit, when
Bit 9 set, causes an interrupt to be generated when
the TxFIFO buffer is half empty and the THEN
bit is set.
13-8
SPI 1 Interrupt Control/Status Register
13 12 11 10
RHE RRE TFE
N N N N
rw rw rw rw
0 0 0 0
Description
MC68VZ328 User's Manual
9 8 7 6
THE TEE B R
N N O O
rw rw rw rw rw
0 0 0 0
0x0000
0 = Disable bit count overflow interrupt.
1 = Enable bit count overflow interrupt.
0 = Disable RxFIFO overflow interrupt.
1 = Enable RxFIFO overflow interrupt.
0 = Disable RxFIFO full interrupt enable.
1 = Enable RxFIFO full interrupt enable.
0 = Disable half interrupt enable.
1 = Enable half interrupt enable.
0 = Disable data ready interrupt enable.
1 = Enabled data ready interrupt enable.
0 = Disable TxFIFO full interrupt.
1 = Enable TxFIFO full interrupt.
0 = Disable TxFIFO half interrupt.
1 = Enable TxFIFO half interrupt.
0x(FF)FFF706
BIT
5 4 3 2 1
R R R T T
F H R F H
rw rw rw rw
0 0 0 0 0
Setting
0
TE
rw
0