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support program memory expansion. The DPAGE and EPAGE registers are not con-
trolled by dedicated CPU12 instructions. These registers can be larger or smaller than
eight bits in various M68HC12 derivatives.
Typically, each of the overlay windows also has an associated control bit to enable
memory expansion through the appropriate window. Memory expansion is generally
disabled out of reset, so control bits must be written to enable the address translation
logic.
10.5 Using Chip-Select Circuits
M68HC12 chip-select circuits can be used to preclude ambiguities in memory-map-
ping due to the operation of internal address translation logic. If built-in chip selects are
not used, take care to use only overlay pages which produce unique addresses on the
external address lines.
M68HC12 derivatives typically have two or more chip-select circuits. Chip-select func-
tion is conceptually simple. Whenever an access to a pre-defined range of addresses
is made, internal MCU circuitry detects an address match and asserts a control signal
that can be used to enable external devices. Chip-select circuits typically incorporate
a number of options that make it possible to use more than one range of addresses
for matches as well as to enable various types and configurations of external devices.
Chip-select circuits used in conjunction with the memory-expansion scheme must be
able to match all accesses made to addresses within the appropriate program overlay
window. In the case of the program expansion window, the range of addresses occu-
pies the 16-Kbyte space from $8000 to $BFFF. For data and extra expansion win-
dows, the range of addresses varies from device to device. The following paragraphs
discuss a typical implementation of memory expansion chip-select functions in the
system integration module. Implementation will vary from device to device within the
M68HC12 family. Please refer to the appropriate device manual for details.
10.5.1 Program Memory Expansion Chip-Select Controls
There are two program memory expansion chip-select circuits, CSP0 and CSP1. The
associated control register contains eight control bits that provide for a number of sys-
tem configurations.
10.5.1.1 CSP1E Control Bit
Enables (1) or disables (0) the CSP1 chip select. The default is disabled.
10.5.1.2 CSP0E Control Bit
Enables (1) or disables (0) the CSP0 chip select. The default is enabled. This allows
CSP0 to be used to select an external memory that includes the reset vector and start-
up initialization programs.
CPU12
REFERENCE MANUAL
MEMORY EXPANSION
MOTOROLA
10-5
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