Pwm 2 Period Register; Table 15-6 Pwm 2 Period Register Description - Motorola MC68VZ328 User Manual

Table 15-5. PWM 2 Control Register Description (Continued)
Name
PIN Pin Status Indicator—This bit indicates the current status of the
Bit 7 PWM.
Reserved Reserved
Bit 6
POL Output Polarity—This bit controls the PWM output polarity.
Bit 5
PWMEN PWM Enable—This bit enables PWM 2.
Bit 4
Reserved Reserved
Bit 3
CLKSEL Clock Selection—These bits select the output of the divider
Bits 2–0 chain.
15.5.2

PWM 2 Period Register

This register controls the period of PWM 2. When the counter value matches the value, an interrupt is
generated and the counter is reset to start another period. The register bit assignments are shown in the
following register display. The register settings are described in Table 15-6.
PWMP2
BIT
14
15
TYPE rw rw
0 0
RESET
Name
PERIOD Period—This field represents the pulse-width modulator's period control value.
Bits 15–0
There is an special case: when the register is set to $00, the output will
never go high. The pulse signal duty cycle will be 0 percent.
Description
PWM 2 Period Register
13 12 11 10
rw rw rw rw
0 0 0 0
Table 15-6. PWM 2 Period Register Description
Description
NOTE:
Pulse-Width Modulator 1 and 2
9 8 7 6 5
PERIOD
rw rw rw rw rw
0 0 0 0 0
0x0000
PWM 2
Setting
0 = PWM output is high.
1 = PWM output is low.
This bit is reserved and
should be set to 0.
0 = Normal polarity.
1 = Inverted polarity.
0 = PWM 2 disabled.
1 = PWM 2 enabled.
This bit is reserved and
should be set to 0.
000 = Divide by 4.
001 = Divide by 8.
010 = Divide by 16.
011 = Divide by 32.
100 = Divide by 64.
101 = Divide by 128.
110 = Divide by 256.
111 = Divide by 512.
0x(FF)FFF512
BIT
4 3 2 1
0
rw rw rw rw rw
0 0 0 0 0
Setting
None
15-9